r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 509

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 21.10
(1)
(5)
(7)
(3)
Preliminary document
Specifications in this document are tentative and subject to change.
Sample Flowchart for Data Reception (MST = 1) (Clock Synchronous Communication
Mode)
Read receive data in SIRDR register
SICR1 register
Read receive data in SIRDR register
SICR1 register
Read receive data in SIRDR register
Read ORER bit in SISR register
Read RDRF bit in SISR register
No
Read ORER bit in SISR register
Read RDRF bit in SISR register
No
(2)
(4)
(6)
SIER register
Dummy read SIRDR register
ORER = 1 ?
ORER = 1 ?
RDRF = 1 ?
RDRF = 1 ?
Initialization
received?
Last data
No
Start
End
Yes
No
No
Yes
RCVD bit  1
RCVD bit  0
RE bit  0
Yes
Yes
Yes
processing
Overrun
error
(1) After setting each register for the synchronous serial
(2), (6) If a receive error occurs, perform error
(3) Confirm that the RDRF bit is 1. If the RDRF bit is
(4) Determine whether the currently outputting clock is
(5) While receiving the last 1 byte of data, set the
(7) Confirm that the RDRF bit is 1. To complete the
communication unit, the receive operation is started
by performing a dummy read of the SIRDR register.
set to 1, read the receive data in the SIRDR
register. When the SIRDR register is read, the
RDRF bit is automatically set to 0.
the last 1 byte of data to be received.
If so, set the clock to stop after the data is
received.
RCVD bit in the SICR1 register to 1 before reading
the [last frame - 1] of the data and then stop the
clock after the data is received.
receive operation, set the RCVD bit to 0 and the RE
bit to 0 before reading the last 1 byte of data.
If the SIRDR register is read without setting the RE
bit to 0, the receive operation is restarted again.
processing after reading the ORER bit. Then
set the ORER bit to 0. Transmission/reception
cannot be restarted while the ORER bit is 1.
21. Clock Synchronous Serial Interface
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