r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 371

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
18.2.15 Timer RE2 Interrupt Flag Register (TREIFR) in Real-Time Clock Mode
TRECR register
RTCRST bit in
ALIF Bit (Alarm interrupt flag)
After reset by
Bit
b0
b1
b2
b3
b4
b5
b6
b7
After Reset
[Conditions for setting to 0]
• When 0 is written to this bit after reading it. If the result of reading this bit is 1, writing 0 to this bit will set it
• When an interrupt from the DTC is automatically cleared.
[Condition for setting to 1]
• The contents of the timer RE2 alarm register
Notes:
to 0.
Alarm Function).
If the result of reading this bit is 0, writing 0 to this bit will not change its value. If this bit changes from 0 to 1
after the read, the bit will remain 1 even if 0 is written. Writing 1 has no effect.
To confirm the match, set an enable bit in the timer RE2 alarm registers
Address 0017Ah
Symbol TADJSF
RSTADJ Second counter reset adjustment bit When 1 is written to this bit, the value of the
1. Timer RE2 alarm registers: TREAMN, TREAHR, and TREAWK
2. Timer RE2 data registers: TREMIN, TREHR, and TREWK
ADJ30S 30-second adjustment bit
TADJSF Correction status flag
Symbol
RTCF
ALIE
ALIF
—
—
Bit
Preliminary document
Specifications in this document are tentative and subject to change.
Alarm interrupt flag
Real-time clock periodic interrupt flag
Alarm interrupt enable bit
Nothing is assigned. The write value must be 0. The read value is 0.
b7
0
0
b6
—
0
0
Bit Name
b5
—
0
0
RSTADJ ADJ30S
b4
0
0
(1)
and the timer RE2 data register
0: No interrupt requested
1: Interrupt requested
0: Alarm interrupt disabled
1: Alarm interrupt enabled
When 1 is written to this bit, the value of the
TRESEC register changes as follows.
When TRESEC register value  29: TRESEC  00
When TRESEC register value  30:
The read value is 0.
TRESEC register is set to 00 and the internal
counter is initialized.
The read value is 0.
0: No correction
1: Being corrected
b3
0
0
TRESEC  00, TREMIN  TREMIN + 1
ALIE
b2
0
0
Function
(1)
to 1.
RTCF
b1
0
0
(2)
ALIF
match (refer to 18.3.5
b0
0
0
Page 340 of 725
18. Timer RE2
R/W
R/W
R/W
R/W
W
W
—
R