r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 460

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 20.16
20.3.3.3
The transfer clock is used to transmit and receive data as is shown in Figure 20.14 Transfer to U2RB Register
and Interrupt Timing.
The CSC bit in the U2SMR2 register is used to synchronize an internally generated clock (internal SCL) and an
external clock supplied to the SCL2 pin. When the CSC bit is set to 1 (clock synchronization enabled), if a
falling edge on the SCL2 pin is detected while the internal SCL is high, the internal SCL goes low. The value of
the U2BRG register is reloaded and counting of the low-level intervals starts. If the internal SCL changes state
from low to high while the SCL2 pin is low, counting stops. If the SCL2 pin goes high, counting restarts.
In this way, the UART2 transfer clock is equivalent to AND of the internal SCL and the clock signal applied to
the SCL2 pin. The transfer clock works from a half cycle before the falling edge of the internal SCL 1st bit to
the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The SWC bit in the U2SMR2 register determines whether the SCL2 pin is held low or released from low output
at the falling edge of the 9th bit of the clock.
If the SCLHI bit in the U2SMR4 register is set to 1 (enabled), SCL2 output is turned off (placed in the high-
impedance state) when a stop condition is detected.
Setting the SWC2 bit in the U2SMR2 register to 1 (low output) makes it possible to forcibly output a low-level
signal from the SCL2 pin even while sending or receiving data. Setting the SWC2 bit to 0 (transfer clock)
allows the transfer clock to be output from or supplied to the SCL2 pin, instead of outputting a low-level signal.
If the SWC9 bit in the U2SMR4 register is set to 1 (SCL2 pin low output hold enabled) when the CKPH bit in
the U2SMR3 register is 1, the SCL2 pin is held low at the next falling edge after the 9th bit of the clock. Setting
the SWC9 bit to 0 (SCL2 pin low output hold disabled) releases the SCL2 pin from low output.
(1) Slave Mode
(2) Master Mode
CKDIR = 0 (internal clock)
CKDIR = 1 (external clock)
Preliminary document
Specifications in this document are tentative and subject to change.
STSPSEL Bit Functions
Transfer Clock
STSPSEL bit 0
STSPSEL bit
SDA2
SDA2
SCL2
SCL2
Set STAREQ = 1
(start)
Set to 1 by a
program
Start condition detection
interrupt
Set to 0 by a
program
Start condition detection
interrupt
1st bit 2nd bit 3rd bit
1st bit 2nd bit 3rd bit
5th bit 6th bit 7th bit 8th bit 9th bit
Set STPREQ = 1
(start)
5th bit 6th bit 7th bit 8th bit 9th bit
Stop condition detection
interrupt
Set to 1 by a
program
Stop condition detection
interrupt
20. Serial Interface (UART2)
Set to 0 by a
program
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