r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 480

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.1.2
Table 21.2
Transfer data format
Communication modes
I/O pins
Transfer clocks
Receive error detection
Multimaster error detection
Interrupt sources
Selectable functions
The synchronous serial communication unit (SSU) supports clock synchronous serial data communication. The
SSU consists of a channel: SSU_0. This chapter describes these channels as SSU unless there are differences
among them.
Table 21.2 lists the Synchronous Serial Communication Unit Specifications and Figure 21.1 shows the
Synchronous Serial Communication Unit Block Diagram (i = 4, 8, 16, 32, 64, 128, or 256).
Synchronous Serial Communication Unit (SSU)
Item
Preliminary document
Specifications in this document are tentative and subject to change.
Synchronous Serial Communication Unit Specifications
Transfer data length: 8 to 16 bits
• Clock synchronous communication mode
• 4-wire bus communication mode (including bidirectional communication)
SSCK (I/O): Clock I/O pin
SSI (I/O): Data I/O pin
SSO (I/O): Data I/O pin
SCS (I/O): Chip select I/O pin
• When the MST bit in the SICR1 register is 0 (slave mode)
• When the MST bit in the SICR1 register is 1 (master mode)
• The clock polarity and phase can be selected.
• Overrun error detection
• Conflict error detection
5 (transmit end, transmit data empty, receive data full, overrun error, and conflict
error)
• Data transfer direction
• SSCK clock polarity
• SSCK clock phase
- Master or slave device can be selected.
- Continuous transmission and reception of serial data are supported because the
External clock (input from the SSCK pin)
Internal clock (selectable among f1/256, f1/128, f1/64, f1/32, f1/16, f1/8, and f1/4,
output from the SSCK pin)
Indicates an overrun error has occurred during reception and reception is
terminated in error. When the next serial data reception is completed while the
RDRF bit in the SISR register is 1 (data present in the SIRDR register), the
ORER_AL bit in the SISR register is set to 1 (overrun error).
When starting a serial communication while the MS bit in the SIMR2 register is 1
(4-wire bus communication mode) and the MST bit in the SICR1 register is 1
(master mode), the CE_ADZ bit in the SISR register is set to 1 (conflict error) if the
SCS pin input is low.
When the SCS pin input changes from low to high during transfer while the MS bit
in the SIMR2 register is 1 (4-wire bus communication mode) and the MST bit in the
SICR1 register is 0 (slave mode), the CE_ADZ bit in the SISR register is set to 1.
MSB first or LSB first can be selected.
The level (low or high) when the clock stops can be selected.
The edge for data change and data download can be selected.
shift, transmit, and receive registers are independent.
Description
21. Clock Synchronous Serial Interface
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