r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 488

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.2.3
Note:
21.2.4
Notes:
b15 to b0 Store the transmit data.
b15 to b0 Store the receive data.
After Reset
After Reset
After Reset
After Reset
1. The data transfer length of 9 bits or more (b8 to b15) is used only with the SSU function. When setting the SSU
1. When the ORER_AL bit in the SISR register is set to 1 (overrun error), the SIRDR register retains the data
2. The SSU data transfer length of 9 bits or more (b8 to b15) is used only with the SSU function. When setting the
3. Read the SIRDR register when the RDRF bit is 1 (data present in the SIRDR register).
Bit
Bit
Address 000E2h (SITDR_0)
Address 000E4h (SIRDR_0)
data transfer length to 9 bits or more using the SSBR register, access the SITDR register in 16-bit units.
When using 8-bit access, the transmit operation will not be started even if the higher byte (b15 to b8) is
accessed. When the lower byte (b7 to b0) is accessed, TDRE is negated and the transmit operation starts.
received before an overrun error occurs. The receive data (data in the SISDR register) when an overrun error
occurs is discarded.
SSU data transfer length to 9 bits or more using the SSBR register, access the SIRDR register in 16-bit units.
When the SIRDR register is accessed in 8-bit units, the RDRF bit in the SISR register is also set to 0 (no data in
the SIRDR register).
Symbol
Symbol
Symbol
Symbol
Bit
Bit
Bit
Bit
SI Transmit Data Register (SITDR)
When it is detected that the SISDR register is empty, the transmit data stored in this register is
transferred to the SISDR register and transmission is started.
If the next transmit data has been written to the SITDR register during the data transmission from
the SISDR register, the data can be transmitted consecutively.
When the MLS bit in the SIMR1 register is 1 (data transfer with LSB first), the data with inverted
MSB and LSB is read after writing to the SITDR register.
SI Receive Data Register (SIRDR)
When 1 byte of data has been received by the SISDR register, the receive data is transferred to
the SIRDR register and the receive operation is completed. At this time, the next receive operation
is enabled.
Continuous reception is enabled using registers SISDR and SIRDR.
Preliminary document
Specifications in this document are tentative and subject to change.
b15
b15
b7
b7
—
—
—
—
1
1
1
1
b14
b14
b6
b6
—
—
—
—
1
1
1
1
(1, 2, 3)
(1)
b13
b13
b5
b5
—
—
—
—
1
1
1
1
b12
b12
b4
b4
—
—
—
—
1
1
1
1
Function
Function
b11
b11
b3
b3
—
—
—
—
1
1
1
1
b10
b10
b2
b2
—
—
—
—
1
1
1
1
21. Clock Synchronous Serial Interface
b1
b9
b1
b9
—
—
—
—
1
1
1
1
b0
b8
b0
b8
—
—
—
—
1
1
1
1
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