r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 510

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
21.3.2.4
Figure 21.11 shows an Operation Example during Data Transmission/Reception (Clock Synchronous
Communication Mode, 8-Bit SSU Data Transfer Length).
Data transmission/reception is an operation combining data transmission and reception, which were described
earlier.
Transmission/reception is started by writing data to the SITDR register. While the TDRE bit in the SISR
register is 1 (data is transferred from registers SITDR to SISDR), if the last transfer clock (the data transfer
length can be set from 8 to 16 bits using the SSBR register) rises or the ORER_AL bit in the SISR register is set
to 1 (overrun error), the transmit/receive operation is stopped.
When switching from transmit mode (TE_NAKIE = 1) or receive mode (RE_STIE = 1) to transmit/receive
mode (TE_NAKIE = RE_STIE = 1), set the TE_NAKIE bit in the SIER register to 0 and RE_STIE bit to 0 once
before making the change. After confirming that the TEND bit in the SISR register is 0 (the TDRE bit is 0 when
the last bit of transmit data is transmitted), the RDRF bit in the SISR register is 0 (no data in the SIRDR
register), and the ORER_AL bit in the SISR register is 0 (no overrun error), set bits TE_NAKIE and RE_STIE
to 1.
Figure 21.12 shows a Sample Flowchart for Data Transmission/Reception (Clock Synchronous Communication
Mode).
When cancelling transmit/receive mode after this mode is used (TE_NAKIE = RE_STIE = 1), a clock may be
output if transmit/receive mode is cancelled after reading the SIRDR register. To avoid any clock outputs, use
either of the following procedures:
• Set the RE_STIE bit to 0 and then set the TE_NAKIE bit to 0.
• Set bits TE_NAKIE and RE_STIE to 0 at the same time.
When switching to receive mode (TE_NAKIE = 0 and RE_STIE = 1) after that, write 1 to the SIRST bit and
then set this bit to 0 to initialize the SSU control block and the SISDR register before setting the RE_STIE bit to
1.
Preliminary document
Specifications in this document are tentative and subject to change.
Data Transmission/Reception
21. Clock Synchronous Serial Interface
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