r5f21368sdfp Renesas Electronics Corporation., r5f21368sdfp Datasheet - Page 464

• Manufacturer Part Number: r5f21368sdfp
• Description: Renesas Mcu R8c Family / R8c/3xt-a Series
• Manufacturer: Renesas Electronics Corporation.

Under development
R8C/36T-A Group
R01UH0240EJ0001 Rev.0.01
Apr 28, 2011
Figure 20.20
20.3.3.10 SDA2 Pin Output Disable Function
(3) SCL2 Pin Low Output Hold Function 3
If its own address differs from the address specified by the master, a slave must turn off (high impedance)
SDA2 pin output.
UART2 achieves this by turning off SDA2 pin output by setting 1FFh to the transmit buffer register every nine
clocks (every time a receive interrupt request is generated) of SCL. SDA2 pin output can also be turned off
using the SDA2 pin output disable function of UART2. This function is enabled by setting the SDHI bit to 1,
which allows UART2 SDA2 pin output to be set to high impedance without setting 1FFh to the transmit buffer
register. This function is disabled by setting the SDHI bit to 0.
When the I
in synchronization with the 9th bit.
At this time, the slave checks for an acknowledge. If an acknowledge is detected, transmission continues
(next transmit data is set). If an acknowledge is not detected, transmission ends.
SCL2 Pin Low Output Hold Function 3 of UART2 was created for this process. By using this function,
a low level is output to the SCL2 pin of UART2 in synchronization with the SCL of the final bit going low
after the first 9 bits (ACK/NACK) of data are received. This forces the master into a wait state. The
function can also continue or end transmission after the acknowledge determination processing by
software is completed.
This function is enabled by setting the SWC9 bit to 1, and disabled by setting it to 0.
After the SCL2 pin has been driven low by this function, it can be released from low level by setting the
SWC9 bit to 0. This function should only be used when the MCU is being used as a slave. Figure 20.20
shows the Timing of SCL2 Pin Low Output Hold Function 3.
Transmit SCL
Master SCL
Preliminary document
Specifications in this document are tentative and subject to change.
Timing of SCL2 Pin Low Output Hold Function 3
SWC9
2
C bus performs slave transmission, the master generates (or doesn't generate) an acknowledge
8th bit
9th bit
The SCL2 pin is held
low here
(Acknowledge determination
1st bit
continue/end processing)
processing and transmit
Setting the SWC9 bit to 0 frees
the SCL2 pin from low output
20. Serial Interface (UART2)
2nd bit
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