MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 81

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
15:14
15:12
Bit #
Bit #
11:8
13
12
11
10
9
8
7
6
5
4
3
2
...
7
6
1
0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
R/W
R/W
R/W
R/W
R/W
R
R
...
R
Unused. Read all 0’s
Reserved.
Parity Bit. The incoming Parity Bit is odd parity when 0, even parity when 1.
Override for the tristate of the cell available. When set UTxClav’s value is always driven.
FIFO-full override. When set the Tx UTOPIA interface will continue to accept cells even
when it does not have room for them. These cells are then discarded.
UTOPIA loopback mode indicator. When set the Tx UTOPIA will accept cells and loop these
back to the Rx UTOPIA interface. The Rx UTOPIA interface will then output these cells.
Stand-by mode bit. When set the TX UTOPIA will continue to operate normally, but all of the
interface’s output pins will be in high impedance mode.
Selects between 16- and 8-bit mode for the Utopia bus. A 0 selects a 16-bit wide bus and a
1 selects an 8-bit wide bus.
A 1 resets the state of the Input UTOPIA Controller. Write 0 for normal operation.
Reserved. Write 0 for normal operation.
Unassigned Cell Filter. A 1 signifies that the Unassigned
will be discarded. The Unassigned/Idle cell counter is incremented for each cell discarded.
Idle Cell Filter. A 1 signifies that the Idle
The Unassigned/Idle cell counter is incremented for each cell discarded.
ATM Forum Polynomial. A 1 disables the addition of the ATM Forum Polynomial calculation
on the HEC calculated as per I.432. A 0 means that the coset value is included in the HEC
value.
Unused. Reads all 0’s.
Reserved. Write all 0’s for normal operation.
Enable UTOPIA PHY address of IMA Group 7. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 6. A 1 enables the PHY port Address.
...
Enable UTOPIA PHY address of IMA Group 1. A 1 enables the PHY port Address.
Enable UTOPIA PHY address of IMA Group 0. A 1 enables the PHY port Address.
0x0052 (1 reg)
1 register for all the UTOPIA Input ports.
000X000000000000
0x0051 (1 reg)
1 register to enable the IMA Groups. For MT90222 only groups 0,1,2 and 3 are
used.
0000
Table 15 - UTOPIA Input Group PHY Enable Register
Table 16 - UTOPIA Input Control Register
Zarlink Semiconductor Inc.
MT90222/3/4
81
2
Description
Description
cells coming from the ATM layer will be discarded.
1
cells coming from the ATM layer
Data Sheet