MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 21

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MT90222AG

Manufacturer Part Number
MT90222AG
Description
Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
Manufacturer
Zarlink Semiconductor
Datasheet
MT90224 Pin Description (continued)
AA3,AA4, AA1,Y3
R26,T26,T24,U24
A26, AB25,AC25,
6,D25,B24,C22,C
6,C26,A25,B23,A
4,E24,C23,A24,B
8,D18,C18,A19,B
P26,M26,M24,L2
5,W26,W23,Y24,
H24,G23,F23,D2
H25,G26,G24,F2
H23,G25,F25,E2
R25,T25,U26,V2
N26,M25,L26,K2
P25,N24,M23,L2
B17,C17,A18,B1
,V23,W24,Y25,A
AB24,AD26,
AC21,AD20,
AD19,AD18,
AE22,AF21,
AF20,AF19,
22,D21,C20
22,B21,B20
AE18,AF17
AF18,AD16
21,A21,A20
4,K24,J23,
5,K25,J25,
6,J26,J24,
AB2,AB1
Pin #
AA24,
D16
A17
19
TXRingSync
TXRingData
TXSYNCio
TXRingClk
RXSYNCi
PLLREF
TXCKio
REFCK
Name
RXCKi
[15:0]
[15:0]
[15:0]
[15:0]
[15:0]
DSTi
[1:0]
[3:0]
[7:0]
I/O
I/O TDM Interface Transmit Clock 15-0. This pin is an input or an output as selected by
I/O Transmit Line Frame Pulse 15-0. This pin is an input or an output as selected by
O Output reference to an external PLL.
O TDM Ring TX Clock. Clock output signal used to align the TXRingSync and
O TDM Ring TX Sync. Synchronization output signal used to retrieve data and control
O TDM Ring TX Data[7:0]. Data Bus connecting the TX TDM Ring port to the RX TDM
I
I
I
I
Serial TDM Data Input 15-0. Serial stream which contains receive data. It is aligned
with RXCKi and RXSYNCi. These pins have internal weak pull-downs.
the TDM TX Link Control registers. The TXCK source is software selectable and
can be either one of the sixteen RXCK or one of the four REFCK signals when
defined as output. When defined as input, the proper clock signal is provided to the
input pin. The clock polarity is determined by the TDM TX Link Control registers.
These pins have internal weak pull-downs.
the TDM TX Link Control registers.
It is the frame reference (typically 8 kHz) used as transmit synchronization for the
TDM system interface. When an output, the TXSYNC is generated from the TXCK
signal and is independent from other TXSYNC signals. Two major modes are
available: generic and ST-BUS:
1. For ST-BUS applications, it is a low going pulse (F0), that delimits the 32/64/128
channel frame of the ST-BUS interface at DSTi and DSTo lines.
2. For generic TDM Interfaces, it can be programmed to generate or receive either a
positive or negative pulse polarity that marks the first bit of the TDM system interface.
These pins have internal weak pull-downs.
Receive line Frame Pulse 15-0. It is the frame reference (typically 8 kHz) used as
receive synchronization for the TDM system interface. Two major modes are
available: generic and ST-BUS:
1. For ST-BUS applications, it is a low going pulse (F0), that delimits the 32/64/128
channel frame of the ST-BUS interface at DSTi and DSTo lines.
2. For generic TDM Interfaces, it can be programmed to accept either a positive or
negative pulse polarity that marks the first bit of the TDM system interface. These
pins have internal weak pull-downs.
TDM Interface Receive Clock 15-0. This input line represents the clock for the
receive serial TDM data. The expected frequency value to be received at this input
clock is defined by the user through the RX Link TDM Control register. These pins
have internal weak pull-downs.
Input Reference Clock inputs 3 to 0. Receive the de-jittered transmit clock
reference to be internally routed to the TXCKio transmit clocks. These pins have
internal weak pull-downs.
TXRingData. Should be connected to the RXRingClk input of the next MT90224
device in the Ring. This output is in High Z state if the TDM Ring is not used. NOT 5V
TOLERANT.
from the bytes on TXRingData. Should be connected to the RXRingSync input of the
next MT90224 device in the Ring. This output is in High Z state if the TDM Ring is
not used. NOT 5V TOLERANT.
Ring port. Should be connected to the RXRingData inputs of the next MT90224
device in the Ring. These output are in High Z state if the TDM Ring is not used. NOT
5V TOLERANT.
Zarlink Semiconductor Inc.
MT90222/3/4
TDM Ring Signals
21
Description
Data Sheet

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