MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 119

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
Bit #
Bit #
15:0
15:0
4:3
2
1
0
Type
Type
Type
R/W
R/W
R/W
R/W
R/W
R/W
Multiplex mode select:
00: no multiplexing,
01: multiplex on a per byte basis, 2 links to 1 link. Valid for ST-BUS mode only.
10: multiplex on a per byte basis, 4 links to 1 link. Valid for ST-BUS mode only.
Clock and sync format:
When 0, TDM is in Generic mode: clock is 1x data rate and sync is 1 bit long at beginning
of frame.
When 1, TDM is ST-BUS Format: clock 2x data rate and sync as per ST-BUS format
Clock polarity:
When 0, the data is output/sampled at the falling edge of TXCK
When 1, the data is output/sampled at the rising edge of TXCK
This bit is ignored in ST-BUS Format.
Sync polarity:
When 0, the sync pulse is active low
When 1, the sync pulse is active high.
This bit is ignored in ST-BUS Format.
Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not in
use, the DSTo pin is in High Z mode for the corresponding time slot.
This registers controls time slots 15:0.
Each bit controls if the corresponding time slot is used to carry ATM Traffic. When not in
use, the DSTo pin is in High Z mode for the corresponding time slot.
This registers controls time slots 31:16. For T1 links, bit 8 (timeslot 24) must be zero.
0x0600 - 0x060F (16 reg)
1 reg. per TX link.
0000
0x0610 - 0x061F (16 reg)
Control time slot 15:0
0000
0x0620 - 0x062F (16 reg)
Control time slot 31:16
0000
Table 102 - TDM TX Mapping (timeslots 31:16) Register
Table 101 - TDM TX Mapping (timeslots 15:0) Register
Table 100 - TDM TX Link Control Register (continued)
Zarlink Semiconductor Inc.
MT90222/3/4
119
Description
Description
Description
Data Sheet