MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 34

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

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The MT90222/3/4 can be separated into four major independent blocks and five support blocks.The four major
independent blocks are:
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The five support blocks are:
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2.0
The transmit path corresponds to a cell flow from the ATM Layer towards the PHY Layer. The ATM cell path on the
transmit side starts at the UTOPIA L2 or L1 Interface. Once ATM cells are received at the UTOPIA port, the device
transfers these cells to the transmit block.
The MT90222/3/4 provides ATM cell mapping and transmission convergence blocks to transport ATM cells over a
maximum of sixteen flexible serial interface ports. These serial interface ports communicate with most off-the-shelf
T1/E1/J1 framers, xDSL modems or other low speed link devices.
Each of these serial links can be assigned to either an IMA Group or to a TC link. A single serial link cannot be
assigned to more than one IMA Group. The MT90222 supports up to 4 serial links, while the MT90223 supports up
to 8 serial links and the MT90224 supports up to 16 serial links.
The functional block diagram at Figure 5 illustrates the transmit function of the MT90224.
2.1
In general terms, the MT90222/3/4 transmit input port has the following properties:
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management of the internal re-sequencer RX links (when active)
extraction of the RX IDCR
verification of the delays between links
re-sequencing of ATM cells using external Static RAM
various performance monitoring counters
16-bit microprocessor interface (adaptable to Intel or Motorola interfaces)
the ATM Transmit Path
the ATM Receive Path
the TDM Interface
the UTOPIA Interface
the Counter Block
the Interrupt Block
the Microprocessor Interface Block
the Cell Preprocessor Block
the TDM Ring Block
cell level handshaking complies with the ATM Forum UTOPIA L1 and L2 Specification
behaves like a UTOPIA MPHY Device or Single PHY Device
each port can be enabled or disabled independently
parity (odd or even) can be checked
optionally verifies and then generates the HEC for incoming cells
includes the ATM Forum polynomial when generating the HEC (default option that can be disabled)
Cell In Control
The ATM Transmit Path
Zarlink Semiconductor Inc.
MT90222/3/4
34
Data Sheet