MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 22

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

MT90224 Pin Description (continued)
P2,T3,Y2,AB3,AE
3,D20,C16,A13,A
N25,H26,F26,A2
K23,N4,P23, U4
E2,H1,J1,M3,
D6,D10,D14,
AC16,AE16,
AD12,AD15,
AC19,AD25,
AC06,AC13,
AC17,AC22,
D22,E23,F4,
AF16,AC15,
AE15,AF15,
AA23,AB04,
AD14,AE14
AA25,V26,
6,AF8,
Pin #
AF13
AF14
8,C5
AC1
AD1
C19
D19
A4
D7
A5
B6
C6
B5
C7
B4
RXRingSync
RXRingData
RXRingClk
LatchClk
Name
Reset
TRST
VDD5
Test1
Test2
Test3
Test4
TMS
TDO
V3.3
[7:0]
TCK
TDI
Clk
I/O
O JTAG Test Data Output. Note: TDO is tristated by TRST pin.
O Test2. Must be left not connected (NC).
O Test4. Must be left not connected (NC)
S
S
I
I
I
I
I
I
I
I
I
I
I
I
TDM Ring RX Clock. Clock input signal used to align the RXRingSync and
RXRingData. Should be connected to the TXRingClk input of the previous MT90224
device in the Ring. There is an internal weak pull-down on this input. NOT 5V
TOLERANT.
TDM Ring RX Sync. Synchronization input signal used to retrieve data and control
from the bytes on RXRingData. Should be connected to the TXRingSync output of
the previous MT90224 device in the Ring. There is an internal weak pull-down on
this input. NOT 5V TOLERANT.
TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the TX TDM
Ring port. Should be connected to the TXRingData inputs of the previous MT90224
device in the Ring. There are internal weak pull-downs on these inputs. NOT 5V
TOLERANT.
System Clock (50 MHz nominal). In the MT90224, this clock is used for all internal
operations of the device.
Counter Latch Clock. The clock present at this input can be divided internally to
produce the latch signal for the internal counters. Refer to the Counter Transfer
Command register for more details. This pin has an internal pull-down.
System Reset. This is an active low input signal. It causes the device to enter the
initial state. The Clk signal must be active to reset the internal registers.
JTAG Test Clock. TCK should be pulled down if not used.
JTAG Test Mode Select. TMS is sampled on the rising edge of TCK.
JTAG Test Data Input. This pin has an internal weak pull-down.
JTAG Test Reset (active low). Should be asserted LOW on power-up and during
reset. Must be HIGH for JTAG boundary-scan operation. This pin has an internal
weak pull-down.
Test1. Must be tied Low
Test3. Must be pulled up to V3.3 for normal operation. NOT 5V TOLERANT.
5 Volt supply pin. Connect to a 5 volt supply when interfacing to 5 volt signals,
otherwise, connect to a 3.3 Volt supply.
3.3 Volt supply pin for I/O pins. Connect to a 3.3 Volt supply.
Zarlink Semiconductor Inc.
MT90222/3/4
System Signals
Power Signals
22
Description
Data Sheet