MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 59

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

4.4.2
If a serial link of more than 2.5Mbps but less than 5.0Mbps data rate is required, this mode can be applied. For every
two links in a pair, one is disabled and the other is able to run from 0 up to 5.0 Mb/s. The links that are paired are
pre-determined: link 0 with link 1, link 2 with link 3 and so on. The link that will remain enabled in each pair is also
pre-determined. They are link 0, 2, 4, 6, 8, 10, 12 and 14.
For the pair of link 0 and link 1, the pins associated with link 1 cannot be used and are tri-stated. On the transmit side
of link 0, if the TXCK and TCSYNC are programmed as inputs, TXSYNC must be de-asserted, and the transmitter
will be "free running" and will output serial data continuously. If the TXSYNC is defined as output, a frame pulse is
generated for every 512 TXCK cycles, but can be ignored. The same logic applies for the other pairs.
For any disabled link, its associated registers are all disabled, except for mapping registers that must be set to all
one. No other configuration is necessary for disabled links.
When the link is part of an IMA group, then both links that are paired have to be assigned to the same IMA group
number. This is done by writing to the RX Recombiner Register (0x0201-0x0208).
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
writing the following settings into those enabled links only.
4.4.3
If a serial link of more than 5Mbps but less than 10.0Mbps data rate is required, this mode can be applied. For every
four links in a group, three are disabled and the other is able to run from 0 up to 10.0Mbps. The four links that can
be grouped are pre-determined: link 0, 1, 2, 3 are one group; link 4, 5, 6, 7 are one group and so on. The link that
will remain enabled in each group is also pre-determined. They are link 0, 4, 8 and 12.
For the group of link 0, 1, 2 and 3, the pins associated with link 1, 2 and 3 cannot be used and are tri-stated. On the
transmit side of link 0, if the TXCK and TCSYNC are programmed as inputs, TXSYNC must be de-asserted, and the
transmitter will be "free running" and will output serial data continuously. If the TXSYNC is defined as output, a frame
pulse is generated for every 1024 TXCK cycles, but can be ignored. The same logic applies for the other groups.
For any disabled link, its associated registers are all disabled, except for mapping registers that must be set to all
one. No other configuration is necessary for disabled links.
When the link is part of an IMA group, then the four links that are grouped have to be assigned to the same IMA
group number. This is done by writing to the RX Recombiner Register (0x0201-0x0208).
This mode is selected in TDM TX Link Control (0x0600-0x060F) and TDM RX Link Control (0x0700-0x070F) by
writing the following settings into those enabled links only.
Data rate (bits 6:5) = 10
Multiplex mode (bits 4:3) = 00
Clock and Sync format (bit 2) = 0
Cell delineation mode (bit 10 of TDM RX Link Control only) = 1
Data rate (bits 6:5) = 11
Multiplex mode (bits 4:3) = 00
Clock and Sync format (bit 2) = 0
Cell delineation mode (bit 10 of TDM RX Link Control only) = 1
Non-framed mode - 5.0Mbps
Non-framed mode - 10.0Mbps
Zarlink Semiconductor Inc.
MT90222/3/4
59
Data Sheet