MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 49

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

3.2.12
When an IMA Group is active, the IMA recombiner manages the pointers to the external RAM write and read location
for the stored ATM cells. A cell is read out from the buffer located in the external RAM corresponding to the lowest
link ID (LID) of the IMA Group and placed in the RX IMA UTOPIA FIFO. After a complete cell read, a read pointer is
set to the buffer corresponding to the next LID. At the following IDCR clock cycle, the next available cell is read. ICP
cells are skipped and Filler cells are discarded. This operation is done in a RoundRobin fashion based on the LID
value for each IMA Group link. Faulty conditions (i.e., buffer overflow, excessive delay) are reported through the IRQ
Link Status (0x0435-0x0444) and IRQ IMA Overflow Status (0x0420-0x0427) registers.
3.2.13
The delay values between links reflect the various transit delays though the network. In order to rebuild the original
ATM cell sequence, the link that exhibits less transport delay has to be stored until the data from the slowest link (the
link having the largest transport delay) has arrived. The link that exhibits the largest transport delay will be the link
that requires the least cells to be stored. Conversely, the line that exhibits the least transport delay is the link that
requires the largest number of cells to be stored.
As a network parameter, the delay on a link should be constant. The delay between links should only change when
links are replaced, added to a group (introducing a new greatest or least delay link) or removed from a group
(removing a greatest or least delay link).
Indirect access is provided to internal registers which hold the various link delay values. The link number and delay
type are first selected by writing to the RX Delay Select (0x02AA) register. After 2 system clock cycles, the 11-bit
value in the RX Delay (0x0285) and the RX Delay Link Number (0x0286) registers are updated and can be read.
The valid delay types are: the Maximum Delay over Time, the Current Maximum Delay and the Current
Minimum Delay for an IMA group and the Current Delay values for any link.
The delay values can be converted to time values by multiplying the number of cells by the conversion factor listed
in the Table 5.
Cell Sequence Recovery
Delay Between Links
Table 4 - Differential Delay for Various Memory Configuration
Note: Assuming a Guardband of 4 cells
Memory Size
Table 5 - Conversion Factors Time/Cell (msec)
(Kbytes)
T1 ISDN (23 ch. per frame)
1024Kb
128Kb
256Kb
512Kb
32Kb
64Kb
T1 (24 ch. per frame)
E1 (30 ch. per frame)
Link Type
Zarlink Semiconductor Inc.
MT90222/3/4
T1 links
140
281
16
34
69
8
49
Delay (msec)
Time per cell
E1 links
(msec)
0.288
0.276
0.221
225
112
13
27
55
6
Data Sheet
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