MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 124

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

8.0
Inverse Multiplexing for ATM (IMA) divides a high-bandwidth stream of ATM cells in a round-robin fashion and sends
them over grouped T1/E1/J1 or DSL lines in a logical connection (on public or private networks) and recombines the
cells to recover the original high-bandwidth stream at the receiving end. Zarlink’s MT90222/3/4 is ideally suited to
implement the IMA function.
8.1
Many off-the-shelf T1/E1/J1 framers require the generation of a 1.544 MHz or 2.048 MHz transmit clock reference
signal at an input pin. The MT9042 can generate both of these clocks and the ST-BUS back-plane signals (C4,F0).
Figure 20 provides an example implementation using existing T1/E1/J1 framers and a common 2 Mbps ST-BUS
backplane.
New generation Zarlink framers only require the ST-BUS 4.096 MHz (C4) clock and a Frame Pulse (F0i) at the
transmit interface. An internal PLL generates the required 1.544 MHz or 2.048 MHz transmit clock. Figure 21
provides an example of an IMA implementation based on the Zarlink MT90224 and the Zarlink MT9076 framers. This
configuration supports CTC mode. Although the MT9076 use the ST-BUS format, it is not configured as a common
backplane.
Figure 22 exemplifies an IMA implementation supporting the asynchronous link operation mode. Each T1,E1/J1
framer uses independent clock and synchronization signals which corresponds to ITC mode.
Figure 23 exemplifies an IMA implementation supporting the asynchronous link operation mode. Each T1,E1/J1
framer uses independent clock and synchronization signals.
Figure 24 exemplifies an IMA implementation supporting the asynchronous link operation mode where the TXCLK
signal is provided by the T1 interface. Each T1 framer uses independent clock and synchronization signals.
Address (Hex):
Reset Value (Hex):
Address
Direct access
Offset
(Hex)
3C0
3A0
3E0
60
...
Connecting the MT90222/3/4 to Various T1/E1/J1 Framers
Application Notes
Type
R/W
R/W
R/W
R/W
...
New ICP cell, Link 1
...
New ICP cell, Link 14
Old ICP cell, Link 15
New ICP cell, Link 15
0x0800 - 0x0BFF, 32 Blocks of 32 words (16 bit wide)
Access these locations directly, then use the transfer command
unknown
to copy to internal memory
Table 113 - RX IMA ICP Cell (continued)
Zarlink Semiconductor Inc.
MT90222/3/4
124
Description
Data Sheet