MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 42

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

When the link is configured in TC mode, IDLE cells are transmitted. Writing to the TDM TX Link Control
(0x0600-0x060F) registers either turns off the transmitter or reconfigures the link into another mode.
2.5
A maximum of sixteen independent serial interfaces can be configured in TC mode (16 for the MT90224, 8 for the
MT90223 and 4 for the MT90222). Figure 6 gives a functional block diagram of the transmitter in Transmission
Convergence (TC) mode.
ATM cells received from the ATM port are placed in a TX Link UTOPIA FIFO, waiting to be transmitted. If the
Idle/Unassigned cell removal option is selected, these cells are dropped. If the TX LINK UTOPIA FIFO is empty, an
Idle cell is sent to the output link. The content of the Idle cell is pre-initialized with the header bytes set at 0x00,
0x00, 0x00 and 0x01. The payload bytes are set to 0x6A.
TX LINK FIFO Length Definition (0x008B-0x0092) registers are used to set the TX Link UTOPIA FIFO size. The
total number of cells in all the TX Link UTOPIA FIFOs, TX IMA UTOPIA FIFO and TX Link FIFO (includes the links
used in IMA Mode and the links used in TC Mode) is limited to 118.
Idle Cells are transmitted on the TC serial interface until the bit corresponding to the link in the UTOPIA Input Link
PHY Enable (0x0050) register is set. Then, the ATM User cells are transferred from the Input UTOPIA port to the
TX serial port.
3.0
The receive path corresponds to the cell flow from the PHY (serial TDM) interfaces to the ATM UTOPIA Interface.
The MT90222/3/4 provides cell delineation and optional cell filtering to discard Unassigned or Idle cells on each
link. The incoming cells are stored in the external RAM, required in IMA mode, to perform cell recovery due to delay
variation between the links introduced by the network.
3.1
This block provides the circuitry necessary to perform functions such as Cell Delineation (CD), cell payload
de-scrambling, HEC verification and filtering of Idle (non-IMA) cells. The CD circuit delineates ATM cells received
from the payload of the T1, E1,J1 or DSL frame through the flexible TDM Interface.
When performing delineation, valid HEC calculations are interpreted to indicate cell boundaries. The CD circuit
performs a sequential hunt for a correct HEC sequence. While performing this hunt, the cell delineation state
machine is in the HUNT state. Figure 7 depicts a state diagram of the cell delineation operation.
ATM In
ATM Transmit Path in TC Mode
Cell Delineation Function
The ATM Receive Path
Figure 6 - Functional Block Diagram of the Transmitter in TC Mode (For Link[N], 0
Output Controller and
Cell_In_Control
Cell Distribution
Zarlink Semiconductor Inc.
MT90222/3/4
42
Tx Link UTOPIA FIFO[N]
Transmitter
Cell RAM
P/S
Data Sheet
Serial
Streams
Link [N]
N
15)