MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 44

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

While the cell delineation state machine is in the SYNC state, the verification circuit implements the state machine
shown in Figure 8.
In normal operation, the HEC verification state machine remains in the ’correction’ state. Incoming cells containing
no HEC errors are passed to the receive IMA block (RX IMA). Incoming single-bit errors can be corrected if required
by the application (i.e., single bit error correction can be enabled or disabled).
After correction (when enabled), the resulting ATM cell is passed to the ICP Processor block for IMA sequencing
control (IMA mode) or Rx Link UTOPIA FIFO (TC mode).
If a single or multi bit error occurs, the state machine transitions to the ’detection’ state. When a cell with a good
HEC is detected, the state machine returns to the ’correction’ state. The HEC calculation normally includes the ATM
FORUM polynomial (X
Link Control (0x00C0-0x00C7) register.
3.1.1
When a serial TDM stream is used with a sync signal such as a TDM Frame Pulse, byte alignment is guaranteed.
As a result, the hunt algorithm searches for the cell boundary based on a predefined number of bytes. If it fails, the
hunt algorithm shifts one byte and tries again.
3.1.2
When a serial TDM stream is used without a sync signal, byte alignment is not guaranteed. The hunt algorithm
searches for the cell boundary based on a predefined number of bytes. If it fails, the hunt algorithm shifts one bit and
tries again. When the hunt algorithm succeeds, it will have determined both the cell boundary and the byte alignment.
3.1.3
The CD circuit can de-scramble the cell payload field. The de-scrambling algorithm can be enabled or disabled using
bit 5 or 13 of the RX Link Control (0x00C0-0x00C7) registers.
The MT90222/3/4 can be programmed, using the RX Link Control (0x00C0-0x00C7) registers, to discard received
ATM cells with HEC errors using bits 2 and 10.
HEC error correction is optional and can be enabled by the CPU. When the option to correct an incoming HEC value
with 1 bit error is selected, the HEC is corrected and the cell is not counted as a cell with a bad HEC. If the option to
remove the cells that are received with a bad HEC is selected, then the incoming cells are replaced by a Filler cell
(in IMA mode) or discarded (in TC mode). The counter is not incremented if the HEC value is corrected, when the
option is enabled.
Incoming Idle and Unassigned cells can be detected and dropped automatically.
(PRESYNC State)
Correct HCS’s
Consecutive
DELTA
Cell Delineation with Sync signal
Cell Delineation without Sync signal
De-Scrambling and ATM Cell Filtering
Accepted
Cell
6
+ X
Correction
4
+ X
2
+ 1). The use of the polynomial can be disabled by writing to bit 1 or 9 of the RX
HCS Single Bit Error Detected (corrected or dropped)
Figure 8 - SYNC State Block Diagram
ATM CELL DELINEATION SYNC STATE
HCS Multi-Bit Error Detected (cell discarded)
Zarlink Semiconductor Inc.
MT90222/3/4
No HCS Errors Detected
44
Detection
Discarded
Cell
Incorrect HCS’s
Jump to HUNT
Data Sheet
Consecutive
ALPHA
State