MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 5

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Pin Diagram - MT90223
The MT90223 uses a 384 pin PBGA with a 1.0mm ball pitch.
AA
AB
AC
AD
AE
AF
C
D
G
H
M
N
R
U
W
A
B
E
F
J
K
L
P
T
V
Y
DSTi[14
DSTo[6] TXCKio
RXSYN
DSTi[6]
RXSYN
TXCKio
TXCKio
TXSyn-
RXCKi
VDD5
VDD5
Ci[12]
VDD5 TXSyn-
cio[6]
Ci[6]
[14]
NC
NC
NC
NC
NC
NC
PD
PD
PD
NC
NC
NC
26
[8]
[8]
26
]
RXSYN
DSTi[4]
DSTi[8]
TXSyn-
DSTo[1
DSTo[1
RXCKi
RXCKi
cio[14]
cio[12]
VDD5
VDD5 TXSyn-
VDD5
Ci[14]
VSS
VSS
[10]
[12]
25
NC
NC
NC
NC
NC
NC
NC
PD
PD
PD
NC
25
[6]
2]
0]
RXSYN
RXSYN
DSTi[12
TXCKio
TXCKio
RXCKi
RXCKi
Ci[10]
cio[8]
Ci[4]
VSS
VSS
[14]
[12]
[10]
24
NC
NC
NC
NC
NC
NC
NC
NC
NC
PD
NC
PD
PD
NC
NC
NC
24
[6]
]
RXSYN
DSTi[10
TXSyn-
DSTo[8]
DSTo[1
RXCKi
cio[10]
VDD5 DSTi[2]
VSS
V3.3
Ci[8]
V3.3
V2.5
V3.3
V2.5
V3.3
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
NC
NC
23
PD
23
[4]
4]
]
RXCKi
V3.3
V3.3
NC
NC
PD
NC
22
[2]
22
RXSYN
DSTo[4]
TXCKio
Ci[2]
NC
NC
NC
PD
NC
21
[4]
21
RXSYN
DSTi[0] TXRing-
TXSyn-
RXCKi
VDD5
cio[4]
Ci[0]
20
NC
NC
PD
20
[0]
TXRing-
DSTo[2]
TXCKio
Data[1]
Data[0]
Latch-
VDD5
Test2 TXRing-
Clk
19
PD
19
[2]
Figure 3 - MT90223 Pinout (Bottom View)
TXRing-
TXRing-
TXRing-
TXSyn-
Data[5]
Data[4]
Data[2]
Data[3]
cio[2]
NC
PD
PD
18
18
TXRing-
TXRing-
TXRing-
DSTo[0] TXSyn-
TXCKio
Data[7]
Data[6]
Sync
V2.5
V3.3
NC
17
[0]
17
sr_cs_1 sr_a[1] sr_a[4]
sr_cs_0 sr_a[0] sr_a[3] sr_a[5] sr_a[8] sr_a[12] sr_a[16] sr_d[0] sr_d[3] sr_d[7]
TXRing-
RXRing
RXRing
RXRing
Data[7]
Data[6]
Data[5]
VDD5
cio[0]
VSS
VSS
VSS
VSS
VSS
VSS
Zarlink Semiconductor Inc.
16
Clk
16
MT90222/3/4
RXRing
RXRing
RXRing
Data[4]
Data[3]
Data[2]
sr_we
VDD5 RXRing
VSS
VSS
VSS
VSS
VSS
VSS
15
NC
15
RXRing
RXRing
sr_a[2] sr_a[6] sr_a[10] sr_a[14] sr_a[17] sr_d[1] sr_d[4]
Data[1]
Data[0]
Sync
V3.3
VSS
VSS
VSS
VSS
VSS
VSS
V2.5
14
14
5
or up_rd
RXRing
up_oe
VDD5
up_cs up_a[11
V2.5
VSS
VSS
VSS
VSS
VSS
VSS
V3.3
Clk
13
13
up_a[10
sr_a[7] sr_a[11] sr_a[15] sr_a[18] VDD5
sr_a[9] sr_a[13]
up_r/w
VDD5 up_a[6] up_a[3] up_a[0] up_d[14
up_wr
VSS
VSS
VSS
VSS
VSS
VSS
12
12
or
]
]
up_a[7]
up_a[8] up_a[4] up_a[1] up_d[15
up_a[9] up_a[5] up_a[2] VDD5 up_d[13
VSS
VSS
VSS
VSS
VSS
VSS
11
11
V3.3
V2.5
10
10
sr_d[2] sr_d[5]
up_irq
9
9
NC
8
8
]
]
up_d[10
up_d[11
up_d[12
sr_d[6]
Test3
TCK
7
7
]
]
]
]
up_d[8] up_d[5] up_d[2]
up_d[9] up_d[7]
VDD5 up_d[6] up_d[4] up_d[1]
TDO
V3.3
V3.3
NC
TDI
6
6
TRST
VDD5
TMS
VSS
VSS
5
5
Data[10
Data[14
Data[13
Data[0]
Data[9]
UTxClk UTxEnb
Addr[2]
Addr[4]
REFCK
URxA-
Reset
ddr[2]
Test4
URx-
URx-
URx-
SOC
UTx-
UTx-
UTx-
UTx-
UTx-
VSS
VSS
V3.3
V2.5
V3.3
V2.5
V3.3
V3.3
VSS
NC
NC
[2]
4
4
]
]
]
Data[11]
Data[15
Data[10
Data[1]
Data[5]
Data[7]
URxClk URxEnb URxA-
Data[2]
Data[6]
UTxPar
Addr[3]
REFCK
REFCK
up_d[3] up_d[0]
URxA-
VDD5
VDD5
VDD5
ddr[1]
URx-
URx-
URx-
URx-
URx-
URx-
UTx-
UTx-
UTx-
UTx-
VSS
Clav
VSS
NC
NC
NC
[0]
[3]
3
3
]
]
Data Sheet
Data[12
URxPar VDD5
Data[12
Data[15
Data[0]
Data[3]
Data[8]
Data[1]
Data[3]
Data[8]
Addr[1]
REF[1]
URxA-
VDD5
VDD5
VDD5
URx-
URx-
URx-
URx-
ddr[3]
VSS
UTx-
UTx-
UTx-
UTx-
UTx-
UTx-
Clav
UTx-
PLL-
VSS
NC
NC
NC
NC
NC
2
2
]
]
]
Data[11]
Data[13
Data[14
REFCK
Data[2]
Data[4]
Data[6]
Data[9]
Data[4]
Data[5]
Data[7]
Addr[0]
REF[0]
URxA-
VDD5
ddr[0]
ddr[4]
URx-
URx-
URx-
URx-
URx-
Test1
UTx-
UTx-
UTx-
UTx-
UTx-
UTx-
SOC
UTx-
PLL-
NC
NC
NC
Clk
NC
[1]
1
1
]
]
AA
AB
AC
AD
AE
AF
W
C
D
G
H
M
N
R
U
A
B
E
F
J
K
L
P
T
V
Y