MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 16

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

MT90223 Pin Description (continued)
B17,C17,A18,B1
8,D18,C18,A19,
AC16,AE16,
AF16,AC15,
AE15,AF15,
AD14,AE14
AA3,AA4,
AB2,AB1
AA1,Y3
Pin #
AF13
AF14
AC1
AD1
D16
C19
D19
A17
B19
D7
C6
A4
A5
B6
B5
TXRingSync
RXRingSync
TXRingData
RXRingData
RXRingClk
TXRingClk
LatchClk
PLLREF
REFCK
Name
Reset
TRST
Test1
Test2
TCK
TMS
TDO
[1:0]
[3:0]
[7:0]
[7:0]
TDI
Clk
I/O
O Output reference to an external PLL.
O TDM Ring TX Clock. Clock output signal used to align the TXRingSync and
O TDM Ring TX Sync. Synchronization output signal used to retrieve data and control
O TDM Ring TX Data[7:0]. Data Bus connecting the TX TDM Ring port to the RX TDM
O JTAG Test Data Output. Note: TDO is tristated by TRST pin.
O Test2. Must be left not connected (NC).
I
I
I
I
I
I
I
I
I
I
I
I
Input Reference Clock inputs 3 to 0. Receive the de-jittered transmit clock reference
to be internally routed to the TXCKio transmit clocks. These pins have internal weak
pull-downs.
TXRingData. Should be connected to the RXRingClk input of the next MT90223
device in the Ring. This output is in High Z state if the TDM Ring is not used. NOT 5V
TOLERANT.
from the bytes on TXRingData. Should be connected to the RXRingSync input of the
next MT90223 device in the Ring. This output is in High Z state if the TDM Ring is not
used. NOT 5V TOLERANT.
Ring port. Should be connected to the RXRingData inputs of the next MT90223
device in the Ring. These output are in High Z state if the TDM Ring is not used. NOT
5V TOLERANT.
TDM Ring RX Clock. Clock input signal used to align the RXRingSync and
RXRingData. Should be connected to the TXRingClk input of the previous MT90223
device in the Ring. There is an internal weak pull-down on this input. NOT 5V
TOLERANT.
TDM Ring RX Sync. Synchronization input signal used to retrieve data and control
from the bytes on RXRingData. Should be connected to the TXRingSync output of the
previous MT90223 device in the Ring. There is an internal weak pull-down on this
input. NOT 5V TOLERANT.
TDM Ring RX Data[7:0]. Data Bus connecting the RX TDM Ring port to the TX TDM
Ring port. Should be connected to the TXRingData inputs of the previous MT90223
device in the Ring. There are internal weak pull-downs on these inputs. NOT 5V
TOLERANT.
System Clock (50 MHz nominal). In the MT90223, this clock is used for all internal
operations of the device.
Counter Latch Clock. The clock present at this input can be divided internally to
produce the latch signal for the internal counters. Refer to the Counter Transfer
Command register for more details. This pin has an internal pull-down.
System Reset. This is an active low input signal. It causes the device to enter the
initial state. The Clk signal must be active to reset the internal registers.
JTAG Test Clock. TCK should be pulled down if not used.
JTAG Test Mode Select. TMS is sampled on the rising edge of TCK.
JTAG Test Data Input. This pin has an internal weak pull-down.
JTAG Test Reset (active low). Should be asserted LOW on power-up and during
reset. Must be HIGH for JTAG boundary-scan operation. This pin has an internal
weak pull-down.
Test1. Must be tied Low
Zarlink Semiconductor Inc.
MT90222/3/4
TDM Ring Signals
System Signals
16
Description
Data Sheet