MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 117

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Address
Bit #
15:8
Offset
09- 17
(Hex)
7:0
00
01
02
03
04
05
06
07
08
18
19
Type
R/W
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Unused. Read all 0’s.
Each bit set to ’1’ represent an overflow condition from the IMA Group associated with the
bit. There is one bit for each IMA Group. A bit is set when one or more of the 4 counters
or the RX UTOPIA FIFO associated with an IMA Group overflows.
Byte #
10, 9
12, 11
14, 13
16, 15
18, 17
48, 19
50, 49
51, 52
MSB,
8 blocks of 32 words (16 bits) from 0x0500 to 0x05FF
Access these locations directly then use transfer
These registers need to be initialized for proper operation
4, 3
ATM
LSB
2, 1
6, 5
8, 7
command to copy to internal memory. For MT90222 only groups 0,1,2 and 3 are
used.
0x0457 (1 reg)
1 register for all IMA groups
0000
Table 98 - IRQ IMA Group Overflow Status Register
LSB: Byte 1 (Header 1 byte) of ICP Cell. The value should be set to 0x00
MSB: Byte 2 (Header 2 byte) of ICP Cell. The value should be set to 0x00
LSB: Byte 3 (Header 3 byte) of ICP Cell. The value should be set to 0x00
MSB: Byte 4 (Header 4 byte) of ICP Cell. The value should be set to 0x0B
LSB: HEC is always calculated and inserted by the MT90222/3/4.
MSB: OAM, should be set to either 0x01 or 0x03
LSB: Cell ID, Link ID. The bit 7 (Cell ID) is controlled by the MT90222/3/4, the
Link ID is provided by the TX Link ID Register.
MSB: IMA Frame Sequence Number. Inserted by the MT90222/3/4.
LSB: ICP Cell Offset. Inserted by the MT90222/3/4 based on the Link Offset
register info.
MSB: Link Stuff Indication. Inserted by the MT90222/3/4
LSB: Status & Control Change Indication. Inserted by the MT90222/3/4.
MSB: IMA ID
LSB: Group Status and Control
MSB: Synchronization Information, inserted by the MT90222/3/4
LSB: Tx Test Control
MSB: Tx Test Pattern
LSB: Rx Test Pattern
MSB: Status and Control of links with LID = 0
Status and Control of links with LID in the range 1-30 (Odd numbered byte in
LSB and even numbered byte in MSB)
LSB: Status and Control of links with LID = 31
MSB: Unused, should be set to 0x6A
LSB: End-to-End channel
MSB: Upper 2 bits of the CRC-10. Inserted by the MT90222/3/4
Table 99 - TX IMA ICP Cell Registers
Zarlink Semiconductor Inc.
MT90222/3/4
117
Description
Description
Data Sheet