MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 110

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Address (Hex):
Direct access
Reset Value (Hex):
Address (Hex):
Direct access
Reset Value (Hex):
Bit #
15:8
7:0
Bit #
11:8
7:4
3:0
Type
R/W
R
Type
R/W
R/W
R/W
Unused. Read 0’s.
Each bit set to ’1’ will enable the generation of the interrupt when the corresponding bit in
the IRQ IMA Group Overflow Status register is set. There is one bit for each status bit.
0x0403 - 0x0406 (4 regs)
1 register per 2 TX IMA Groups. IMA Group n is paired with IMA group n+4.For
MT90222 only groups 0,1,2 and 3 are used.
0C0C
0x040B (1 reg)
1 register for all 8 status bits.
0000
Defines the integration period for IMA Group n+4:
1111: Reserved, do not use
1110: 2
.....
0001: 2
0000: 2
Reserved.
Defines the integration period for IMA Group n:
1111: Reserved, do not use
1110: 2
1101: 2
1100: 2
1011: 2
1010: 2
1001: 2
1000: 2
0111: 2
0110: 2
0101: 2
0100: 2
0011: 2
0010: 2
0001: 2
0000: 2
Table 83 - TX IDCR Integration Registers (continued)
Table 84 - IRQ IMA Group Overflow Enable Register
22
22
15
21
20
19
14
11
09
08
18
17
16
13
12
10
09
08
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles (preferred value for E1)
clock cycles (preferred value for T1 - 24 channels)
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles (preferred value for T1 - 23 channels)
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
Zarlink Semiconductor Inc.
MT90222/3/4
110
Description
Description
Data Sheet