MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 138

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

Note
Note 1: t
9.1
The CPU Interface of the MT90222/3/4 supports both the Motorola and Intel timing modes. No Mode Select pin is
required.
With Motorola devices, the Motorola R/W-signal is connected to the UP_R/W pin and the UP_OE pin is tied to
ground. There is no DS signal and the UP_CS signal is taken to access the MT90222/3/4.
AC Electrical Characteristics - External Memory Interface Timing - Write Access
t
t
t
t
t
t
t
t
t
t
CLK
WC
AVWS
AVWH
CSWS
CSWH
WEWS
WEWH
WDS
WDH
Item
‡
: Typical figures are at 25 C, V
CPU Interface Timing
Note: The SR_WE signal stays LOW until a READ cycle is to be performed
System Clock
WC
SR_A[18:0]
SR_D[7:0]
= t
SR_WE
SR_CS
CLK
MT90222/3/4 System Clock Period
Write Cycle Time
Address Setup Time
Address Hold Time
Chip Select Setup Time
Chip Select Hold Time
Write Enable* Setup Time
Write Enable* Hold Time
Data Setup Time
Data Hold Time
Refer to SRAM Control Register to select the number of cycles
- t
CSWS
Figure 30 - External Memory Interface Timing - Write Cycle
Description
DD
=3.3V, and for design aid only: not guaranteed and not subject to production testing
Zarlink Semiconductor Inc.
MT90222/3/4
t
avws
t
t
wds
csws
138
t
wews
Address Valid
Data Valid
12.5 ns
t
19 ns
cswh
t
0 ns
0 ns
1 ns
1 ns
0 ns
0 ns
0 ns
Min
wc
1
20 ns
Typ
t
avwh
t
wdh
‡
t
wewh
t
clk
Data Sheet
9.5 ns
7.5 ns
7.5 ns
9.5 ns
19 ns
Max