MT90222AG Zarlink Semiconductor, MT90222AG Datasheet - Page 60

• Manufacturer Part Number: MT90222AG
• Description: Description = 4 Port Ima & TC PHY For T1, E1 And DSL ;; Package Type = N/a ;; No. Of Pins =
• Manufacturer: Zarlink Semiconductor

4.5
In any framed modes, the Frame signal format can be one of two options. It can be of a generic format (active high
or low during the first bit of the frame) or ST-BUS format (active low at the boundary of the frame). In the generic
modes, the clock polarity can be selected to have a rising or falling edge at the bit boundary.
The TXCK and TXSYNC signals can be either outputs or inputs.
4.6
Two loopback modes are provided where the TDM RX inputs are internally routed back to the TDM TX outputs
(remote loopback) with the RX block fully operational, and where the TDM TX outputs are routed back to the TDM
RX inputs for test purposes (metallic loopback). The TX and RX links have to be programmed in the same mode for
the loopback to operate properly. Bit 8 of the TDM TX Link Control Register (0x0600-0x060F) controls the remote
loopback and bit 8 of the TDM RX Link Control (0x0700-0x070F) register controls the metallic loopback.
To use remote loopback, TXCK and TXSYNC must be configured as output sourcing from the RXCK and RXSYNC
of the same port. The loopback is on a per link basis with the limitation that physical links are paired: i.e. TX link 0 is
connected to RX link 0 and so on.
Besides TDM loopacks, there is also a UTOPIA loopback described in the section 5.7.
4.7
Each serial TDM link has assigned S/P and P/S units. The P/S unit takes a byte from the cell RAM and converts it
to a serial bit stream. The S/P unit takes a byte from the DSTi input and converts it to parallel format for use by the
Cell Delineation block.
P/S and S/P units can be set-up differently on a per port and per direction basis (i.e. the transmit and receive function
of the same port can use different configurations). The following features are supported:
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When the TXCK and TXSYNC signals are outputs, the source for the TXCLK is software selectable from any of the
RXCK inputs or any of the four external REFCKs. The TXSYNC signal is generated from the TXCK and is
independent from (not aligned with) the RXSYNC or other TXSYNC signals.
programming links as T1 or E1
using ST-BUS and Generic TDM modes
enabling/disabling the P/S and S/P units (if they are disabled the associated outputs are Tri-stated)
selecting TDM timeslots as per mapping registers.
independently programming the polarity of RXCK, TXCK, RXSYNC and TXSYNC signals (Generic TDM
mode only)
generating/accepting TXSYNC and TXCLK signals to support most T1 and E1 framers (depending on the
programmed mode)
monitoring RXSYNC signal period and reporting the unexpected occurrence of a synchronization signal
monitoring TXSYNC signal period (when defined as input) and reporting the unexpected occurrence of a
synchronization signal
generating a TXSYNC pulse on every TDM frame when defined as output
Clock formats
TDM Loopback Mode
Serial to Parallel (S/P) and Parallel to Serial (P/S) Converters
Zarlink Semiconductor Inc.
MT90222/3/4
60
Data Sheet