UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 850
UPD78F0838
Manufacturer Part Number
UPD78F0838
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.UPD78F0838.pdf
(917 pages)
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848
Notes 1.
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
Conditional
branch
CPU
control
Instruction
Group
2.
2. This clock cycle applies to the internal ROM program.
When the internal high-speed RAM area is accessed or for an instruction with no data access
When an area except the internal high-speed RAM area is accessed
BT
BF
BTCLR
DBNZ
SEL
NOP
EI
DI
HALT
STOP
Mnemonic
register (PCC).
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
B, $addr16
C, $addr16
Saddr, $addr16
RBn
Operands
Preliminary User’s Manual U19748EJ1V0UD
CHAPTER 28 INSTRUCTION SET
Bytes
3
4
3
3
3
4
4
3
4
3
4
4
3
4
3
2
2
3
2
1
2
2
2
2
Note 1
10
10
10
10
10
8
8
8
8
6
6
8
4
2
6
6
Clocks
Note 2
11
11
11
11
11
11
12
12
12
12
10
9
9
6
6
PC
PC
PC
PC
PC
PC
PC
PC
PC
PC
if(saddr.bit) = 1
then reset(saddr.bit)
PC
then reset sfr.bit
PC
then reset A.bit
PC
then reset PSW.bit
PC
then reset (HL).bit
B
PC
C
PC
(saddr)
PC
RBS1, 0
No Operation
IE
IE
Set HALT Mode
Set STOP Mode
PC
B
C 1, then
1(Enable Interrupt)
0(Disable Interrupt)
PC + 3 + jdisp8 if(saddr.bit) = 1
PC + 4 + jdisp8 if sfr.bit = 1
PC + 3 + jdisp8 if A.bit = 1
PC + 3 + jdisp8 if PSW.bit = 1
PC + 3 + jdisp8 if (HL).bit = 1
PC + 4 + jdisp8 if(saddr.bit) = 0
PC + 4 + jdisp8 if sfr.bit = 0
PC + 3 + jdisp8 if A.bit = 0
PC + 4 + jdisp8 if PSW. bit = 0
PC + 3 + jdisp8 if (HL).bit = 0
PC + 4 + jdisp8
PC + 4 + jdisp8 if sfr.bit = 1
PC + 3 + jdisp8 if A.bit = 1
PC + 4 + jdisp8 if PSW.bit = 1
PC + 3 + jdisp8 if (HL).bit = 1
PC + 2 + jdisp8 if B
PC + 2 + jdisp8 if C
PC + 3 + jdisp8 if(saddr)
CPU
1, then
) selected by the processor clock control
(saddr)
n
Operation
1, then
0
0
0
Z AC CY
Flag
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