UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 847

• Manufacturer Part Number: UPD78F0838
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

Notes 1. When the internal high-speed RAM area is accessed or for an instruction with no data access
Remarks 1. One instruction clock cycle is one cycle of the CPU clock (f
16-bit
operation
Multiply/
divide
Increment/
decrement
Rotate
BCD
adjustment
Bit
manipulate
Instruction
Group
2. When an area except the internal high-speed RAM area is accessed
2. This clock cycle applies to the internal ROM program.
ADDW
SUBW
CMPW
MULU
DIVUW
INC
DEC
INCW
DECW
ROR
ROL
RORC
ROLC
ROR4
ROL4
ADJBA
ADJBS
MOV1
Mnemonic
register (PCC).
AX, #word
AX, #word
AX, #word
X
C
r
saddr
r
saddr
rp
rp
A, 1
A, 1
A, 1
A, 1
[HL]
[HL]
CY, saddr.bit
CY, sfr.bit
CY, A.bit
CY, PSW.bit
CY, [HL].bit
saddr.bit, CY
sfr.bit, CY
A.bit, CY
PSW.bit, CY
[HL].bit, CY
Operands
Preliminary User’s Manual U19748EJ1V0UD
CHAPTER 28 INSTRUCTION SET
Bytes
3
3
3
2
2
1
2
1
2
1
1
1
1
1
1
2
2
2
2
3
3
2
3
2
3
3
2
3
2
Note 1
16
25
10
10
6
6
6
2
4
2
4
4
4
2
2
2
2
4
4
6
4
6
6
4
6
Clocks
Note 2
12
12
6
6
7
7
7
7
8
8
8
8
AX, CY
AX, CY
AX
AX
AX (Quotient), C (Remainder)
r
(saddr)
r
(saddr)
rp
rp
(CY, A
(CY, A
(CY
(CY
A
(HL)
A
(HL)
Decimal Adjust Accumulator after Addition
Decimal Adjust Accumulator after Subtract
CY
CY
CY
CY
CY
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
3
3
0
0
r + 1
r
3
7
word
rp + 1
rp
CPU
A
(saddr.bit)
sfr.bit
A.bit
PSW.bit
(HL).bit
7
0
0
4
A
A
1
(HL)
(HL)
CY
0
7
CY
, A
, A
1
) selected by the processor clock control
X
(saddr) + 1
(saddr)
AX + word
AX
A
A
CY
(HL)
(HL)
CY
0
7
7
0
3
7
, A
, A
CY
4
0
7
3
, (HL)
m
m + 1
, (HL)
word
CY, A
CY, A
Operation
4
0
1
1
3
7
m
m + 1
A
A
0
4
m
m
1
)
)
A
A
1 time
1 time
3
A
A
3
m
m
0
0
)
)
,
,
AX
1 time
1 time
C
Z AC CY
Flag
845