UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 310

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UPD78F0838

Manufacturer Part Number
UPD78F0838
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
308
(i) Operation to write 0 (without conflict with setting)
(ii) Operation to write 0 (conflict with setting)
(2) Operation timing in pulse width measurement mode
(a) Clearing overflow flag
(TPnOVF bit)
(TPnOVF bit)
Overflow flag
Overflow flag
0 write signal
0 write signal
The overflow flag can be cleared to 0 by clearing the TPnOVF bit to 0 with the CLR instruction and by
writing 8-bit data (bit 0 is 0) to the TPnOPT0 register. To accurately detect an overflow, read the TPnOVF
bit when it is 1, and then clear the overflow flag by using a bit manipulation instruction.
Remark
To clear the overflow flag to 0, read the overflow flag to check if it is set to 1, and clear it with the CLR
instruction. If 0 is written to the overflow flag without checking if the flag is 1, the set information of
overflow may be erased by writing 0 ((ii) in the above chart). Therefore, software may judge that no
overflow has occurred even when an overflow actually has occurred.
If execution of the CLR instruction conflicts with occurrence of an overflow when the overflow flag is
cleared to 0 with the CLR instruction, the overflow flag remains set even after execution of the clear
instruction.
set signal
set signal
Overflow
Overflow
n = 0 to 4
L
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Preliminary User’s Manual U19748EJ1V0UD
(iii) Operation to clear to 0 (without conflict with setting)
(iv) Operation to clear to 0 (conflict with setting)
access signal
access signal
(TPnOVF bit)
(TPnOVF bit)
Overflow flag
Overflow flag
0 write signal
0 write signal
set signal
set signal
Overflow
Overflow
Register
Register
L
H
Read
Read
Write
Write

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