UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet
UPD78F0838
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UPD78F0838 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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Preliminary User’s Manual 78K0/Dx2 8-Bit Single-Chip Microcontrollers 78K0/DE2: PD78F0836(A) PD78F0836(A2) PD78F0837(A) PD78F0837(A2) 78K0/DF2: PD78F0838(A) PD78F0838(A2) PD78F0839(A) PD78F0839(A2) PD78F0840(A) PD78F0840(A2) PD78F0841(A) PD78F0841(A2) Document No. U19748EJ1V0UD00 (1st edition) Date Published September 2009 NS 2009 Printed in Japan PD78F0844(A) PD78F0844(A2) PD78F0845(A) PD78F0845(A2) PD78F0842(A) ...
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Preliminary User’s Manual U19748EJ1V0UD ...
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NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between V malfunction. Take care ...
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EEPROM is trademark of NEC Electronics Corporation. Windows, Windows NT and Windows XP are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. HP9000 series ...
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The information contained in this document is being issued in advance of the production cycle for the product. The parameters for the product may change before final production or NEC Electronics Corporation, at its own discretion, may withdraw the product ...
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Readers <R> Purpose Organization How to Read This Manual <R> 6 INTRODUCTION This manual is intended for user engineers who wish to understand the functions of the conventional-specification products of the 78K0/Dx2 and design and develop application systems and programs ...
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Conventions Related Documents Documents Related to Devices 78K0/Dx2 User’s Manual 78K/0 Series Instructions User’s Manual Documents Related to Development Tools (Hardware) (User’s Manuals) <R> QB-78K0DX2 In-Circuit Emulator QB-78K0MINI On-Chip Debug Emulator QB-MINI2 On-Chip Debug Emulator with Programming Function Documents Related ...
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Documents Related to Development Tools (Software) RA78K0 Ver.3.80 Assembler Package Note 1 User’s Manual 78K0 Assembler Package RA78K0 Ver.4.01 Operating Precautions (Notification Document) CC78K0 Ver.3.70 C Compiler Note 2 User’s Manual 78K0 C Compiler CC78K0 Ver. 4.00 Operating Precautions (Notification ...
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CHAPTER 1 OUTLINE ............................................................................................................................ 19 1.1 Features ........................................................................................................................................ 19 1.2 Applications.................................................................................................................................. 20 1.3 Ordering Information ................................................................................................................... 21 1.4 Pin Configuration (Top View)...................................................................................................... 22 1.5 Block Diagram .............................................................................................................................. 27 1.6 Outline of Functions .................................................................................................................... 31 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 40 ...
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Relative addressing..........................................................................................................................101 3.3.2 Immediate addressing ......................................................................................................................102 3.3.3 Table indirect addressing .................................................................................................................103 3.3.4 Register addressing .........................................................................................................................104 3.4 Operand Address Addressing .................................................................................................. 105 3.4.1 Implied addressing ...........................................................................................................................105 3.4.2 Register addressing .........................................................................................................................106 3.4.3 Direct addressing .............................................................................................................................107 3.4.4 Short direct addressing ....................................................................................................................108 3.4.5 ...
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Controlling Clock ....................................................................................................................... 194 5.6.1 Controlling high-speed system clock................................................................................................194 5.6.2 Example of controlling internal high-speed oscillation clock.............................................................199 5.6.3 Example of controlling subsystem clock...........................................................................................201 5.6.4 Controlling internal low-speed oscillation clock ................................................................................203 5.6.5 Clocks supplied to CPU and peripheral hardware............................................................................203 5.6.6 ...
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CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 336 9.1 Functions of Watchdog Timer .................................................................................................. 336 9.2 Configuration of Watchdog Timer ............................................................................................ 337 9.3 Register Controlling Watchdog Timer ..................................................................................... 338 9.4 Operation of Watchdog Timer................................................................................................... 339 9.4.1 Controlling operation of watchdog timer ...........................................................................................339 ...
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Registers to Control Serial Interface IIC0 .............................................................................. 457 2 14 Bus Mode Functions .......................................................................................................... 472 14.4.1 Pin configuration ............................................................................................................................472 2 14 Bus Definitions and Control Methods .............................................................................. 473 14.5.1 Start conditions ..............................................................................................................................473 14.5.2 Addresses ......................................................................................................................................474 ...
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Control Registers ..................................................................................................................... 566 15.8 CAN Controller Initialization ................................................................................................... 601 15.8.1 Initialization of CAN module ...........................................................................................................601 15.8.2 Initialization of message buffer .......................................................................................................601 15.8.3 Redefinition of message buffer.......................................................................................................601 15.8.4 Transition from initialization mode to operation mode ....................................................................602 15.8.5 Resetting error ...
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CHAPTER 17 LCD CONTROLLER/DRIVER....................................................................................... 683 17.1 Functions of LCD Controller/Driver ....................................................................................... 683 17.2 Configuration of LCD Controller/Driver ................................................................................. 686 17.3 Registers Controlling LCD Controller/Driver ........................................................................ 688 17.4 Setting LCD Controller/Driver................................................................................................. 693 17.5 LCD Display Data Memory ...................................................................................................... 694 17.6 Common ...
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CHAPTER 22 MULTIPLIER/DIVIDER................................................................................................... 767 22.1 Functions of Multiplier/Divider ............................................................................................... 767 22.2 Configuration of Multiplier/Divider ......................................................................................... 767 22.3 Register Controlling Multiplier/Divider .................................................................................. 771 22.4 Operations of Multiplier/Divider.............................................................................................. 772 22.4.1 Multiplication operation...................................................................................................................772 22.4.2 Division operation...........................................................................................................................774 CHAPTER 23 POWER-ON-CLEAR CIRCUIT...................................................................................... 776 23.1 Functions ...
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Flash Memory Programming by Self-Programming........................................................... 822 26.11 Boot Swap Function .............................................................................................................. 830 26.12 Creating ROM Code to Place Order for Programmed Flash Product ............................... 832 26.12.1 Procedures for ROM code ordering process using HCU..............................................................832 CHAPTER 27 ON-CHIP DEBUG FUNCTION ...
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A.5 Debugging Tools (Software)..................................................................................................... 896 APPENDIX B NOTES ON TARGET SYSTEM DESIGN ................................................................... 897 APPENDIX C REGISTER INDEX ......................................................................................................... 899 C.1 Register Index (In Alphabetical Order with Respect to Register Names)............................ 899 C.2 Register Index (In Alphabetical Order with Respect ...
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Features Minimum instruction execution time can be changed from high speed (0.1 highspeed system clock) to ultra low-speed (114 s: @ 32.768 kHz operation with subsystem clock) General-purpose register: 8 bits Internal CAN controller (for PD78F0844, 78F0845, 78F0846, 78F0847, ...
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Serial interface: 3 (for 78K0/DE2 (for 78K0/DF2) channels (CAN: 1 channel, UART (LIN (Local Interconnect Network)-bus supported): 1 channel (78K0/DF2 only), Note CSI/UART : 1 channel, CSI: 1 channel (78K0/DF2 only), I Note Select either of the functions ...
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Ordering Information Flash memory version <R> Part Number PD78F0836GBA-GAH-G PD78F0836GBA2-GAH-G PD78F0837GBA-GAH-G PD78F0837GBA2-GAH-G PD78F0838GKA-GAK-G PD78F0838GKA2-GAK-G PD78F0839GKA-GAK-G PD78F0839GKA2-GAK-G PD78F0840GKA-GAK-G PD78F0840GKA2-GAK-G PD78F0841GKA-GAK-G PD78F0841GKA2-GAK-G PD78F0842GKA-GAK-G PD78F0842GKA2-GAK-G PD78F0843GKA-GAK-G PD78F0843GKA2-GAK-G PD78F0844GBA-GAH-G PD78F0844GBA2-GAH-G PD78F0845GBA-GAH-G PD78F0845GBA2-GAH-G PD78F0846GKA-GAK-G PD78F0846GKA2-GAK-G PD78F0847GKA-GAK-G PD78F0847GKA2-GAK-G PD78F0848GKA-GAK-G PD78F0848GKA2-GAK-G PD78F0849GKA-GAK-G PD78F0849GKA2-GAK-G Remark All these ...
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Pin Configuration (Top View) 78K0/DE2 ( PD78F0836, 78F0837, 78F0844, 78F0845) 64-pin plastic LQFP (fine pitch) (10 SMV SS SMV DD P73/SGO/SGOF/BUZ P72/SGOA/PCL P120/EXLVI Note P71/CTxD /<TxD60> Note P70/CRxD /<RxD60/INTPR60> RESET P124/XT2/EXCLKS P123/XT1 FLMD0 P122/X2/EXCLK/OCD0B P121/X1/OCD0A REGC V /EV SS ...
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PD78F0838, 78F0839) 80-pin plastic LQFP (fine pitch) ( SMV SS 2 SMV DD P94/SEG36 3 4 P95/SEG37 ...
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PD78F0840, 78F0841, 78F0846, 78F0847) 80-pin plastic LQFP (fine pitch) (12 1 SMV SS SMV 2 DD P94/SM41 3 4 P95/SM42 P96/SM43 5 P97/SM44/ZPD44 6 P73/SGO/SGOF/BUZ 7 P72/SGOA/PCL 8 P120/EXLVI 9 Note P71/CTxD /<TxD60> 10 Note P70/CRxD /<RxD60/INTPR60> 11 ...
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PD78F0842, 78F0843, 78F0848, 78F0849) 80-pin plastic LQFP (fine pitch) (12 1 SMV SS SMV 2 DD P94/SM41 3 4 P95/SM42 P96/SM43 5 P97/SM44/ZPD44 6 P73/SGO/SGOF/BUZ 7 P72/SGOA/PCL 8 P120/EXLVI 9 Note P71/CTxD /<TxD60> 10 Note P70/CRxD /<RxD60/INTPR60> 11 ...
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Pin Identification ANI0 to ANI7: Analog input AV : Analog reference voltage REF AV : Analog ground SS BUZ: Buzzer output COM0 to COM3: Common output CRxD: Receive data for CAN CTxD: Transmit data for CAN EV : Power supply ...
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Block Diagram 78K0/DE2 ( PD78F0836, 78F0837, 78F0844, 78F0845) TIOP00/P16 16-bit timer/ TIOP01/P04 event counter P0 TIOP10/P15 16-bit timer/ event counter P1 TIOP11/P05 RxD60/P14 or P70 (ISC) TIOP20/P14 (ISC) 16-bit timer/ event counter P2 TIOP21/P06 TIOP30/P13 or P17 (ISC) 16-bit ...
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PD78F0838, 78F0839) TIOP00/P16 16-bit timer/ TIOP01/P04 event counter P0 TIOP10/P15 16-bit timer/ event counter P1 TIOP11/P05 RxD60/P14 or P70 (ISC) TIOP20/P14 or P77 (ISC) 16-bit timer/ event counter P2 TIOP21/P06 RxD61/P11 (ISC) TIOP30/P13 or P17 (ISC) 16-bit timer/ ...
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PD78F0840, 78F0841, 78F0846, 78F0847) TIOP00/P16 16-bit timer/ TIOP01/P04 event counter P0 TIOP10/P15 16-bit timer/ event counter P1 TIOP11/P05 RxD60/P14 or P70 (ISC) TIOP20/P14 or P77 (ISC) 16-bit timer/ event counter P2 TIOP21/P06 RxD61/P11 (ISC) TIOP30/P13 or P17 (ISC) ...
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PD78F0842, 78F0843, 78F0848, 78F0849) TIOP00/P16 16-bit timer/ TIOP01/P04 event counter P0 TIOP10/P15 16-bit timer/ event counter P1 TIOP11/P05 RxD60/P14 or P70 (ISC) TIOP20/P14 or P77 (ISC) 16-bit timer/ event counter P2 TIOP21/P06 RxD61/P11 (ISC) TIOP30/P13 or P17 (ISC) ...
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Outline of Functions 78K0/DE2 without CAN ( PD78F0836, 78F0837) Item Internal Flash memory memory (self-programming Note supported) (bytes) Note High-speed RAM Note Expansion RAM CAN buffer RAM High-speed system clock (oscillation frequency) Internal high-speed oscillation clock (oscillation frequency) Internal ...
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Item CAN Serial Note 1 interface LIN-UART/CSI bus LCD controller/driver (seg com) Sound generator Stepper motor controller/driver (with ZPD) Multiplier/divider Vectored Internal interrupt sources Note 2 External <R> Reset On-chip debug function Supply voltage Operating ambient temperature ...
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CAN ( PD78F0838, 78F0839, 78F0840, 78F0841, 78F0842, 78F0843) Item Internal Flash memory memory (self-programming Note supported) (bytes) Note High-speed RAM Note Expansion RAM CAN buffer RAM High-speed system clock (oscillation frequency) Internal high-speed oscillation clock (oscillation frequency) Internal ...
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Item CAN Serial interface 3-wire CSI LIN-UART Note 1 LIN-UART/CSI bus LCD controller/driver (seg com) Sound generator Stepper motor controller/driver (with ZPD) Multiplier/divider Vectored Internal <R> interrupt sources Note 2 External Reset On-chip debug function Supply voltage ...
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CAN ( PD78F0844, 78F0845) Item Internal Flash memory memory (self-programming Note supported) (bytes) Note High-speed RAM Note Expansion RAM CAN buffer RAM High-speed system clock (oscillation frequency) Internal high-speed oscillation clock (oscillation frequency) Internal low-speed oscillation clock (oscillation ...
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Item CAN Serial Note 1 interface LIN-UART/CSI bus LCD controller/driver (seg com) Sound generator Stepper motor controller/driver (with ZPD) Multiplier/divider Vectored Internal interrupt sources Note 2 External <R> Reset On-chip debug function Supply voltage Operating ambient temperature ...
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CAN ( PD78F0846, 78F0847, 78F0848, 78F0849) Item Internal Flash memory memory (self-programming Note supported) (bytes) Note High-speed RAM Note Expansion RAM CAN buffer RAM High-speed system clock (oscillation frequency) Internal high-speed oscillation clock (oscillation frequency) Internal low-speed oscillation ...
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Item CAN Serial interface 3-wire CSI LIN-UART Note 1 LIN-UART/CSI bus LCD controller/driver (seg com) Sound generator Stepper motor controller/driver (with ZPD) Multiplier/divider Vectored Internal <R> interrupt sources Note 2 External Reset On-chip debug function Supply voltage ...
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Outline of timers An outline of the timer is shown below. Operation Interval timer mode External event counter Function Timer output External trigger pulse output PWM output Pulse width measurement Square-wave output Interrupt source <R> <R> Note In the watch ...
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Pin Function List There are four types of pin I/O buffer power supplies: AV these power supplies and the pins is shown below. Power Supply P20 to P23, P24 to P27 AV REF EV Port pins other than P20 ...
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Port pins 78K0/DE2 ( PD78F0836, 78F0837, 78F0844, 78F0845) <R> Pin Name I/O P00 I/O P01 P02 P03 P04 P05 P06 P07 P10 I/O P11 P12 P13 P14 P15 P16 P17 P20 to P23 I/O P30 I/O P31 P32 P33 ...
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Pin Name I/O P70 I/O Port 7. 4-bit I/O port. Input/output can be specified in 1-bit units. P71 Use of an on-chip pull-up resistor can be P72 specified by a software setting. P73 P80 to P82 I/O Port 8 8-bit ...
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PD78F0838, 78F0839, 78F0840, 78F0841, 78F0842, 78F0843, 78F0846, 78F0847, 78F0848, 78F0849) <R> Pin Name I/O P00 I/O P01 P02 P03 P04 P05 P06 P07 P10 I/O P11 P12 P13 P14 P15 P16 P17 P20 to P27 I/O P30 I/O ...
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Pin Name I/O P70 I/O Port 7. 8-bit I/O port. Input/output can be specified in 1-bit units. P71 Use of an on-chip pull-up resistor can be P72 specified by a software setting. P73 P74 P75 P76 P77 P80 to P82 ...
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Non-port pins 78K0/DE2 ( PD78F0836, 78F0837, 78F0844, 78F0845) <R> Pin Name I/O ANI0 to ANI3 Input AV – REF AV SS BUZ Output COM0 to COM3 Output Note CRxD Input Note CTxD Output EXCLK Input EXCLKS Input EXLVI Input ...
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Table 2-4. Non-port Pins for 78K0/DE2 (2/4) Pin Name I/O RESET Input System reset input RxD60 Input Serial data input to asynchronous serial interface <RxD60> SCK10 I/O Clock input/output for serial interface SCL0 I/O Clock input/output for ...
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Table 2-4. Non-port Pins for 78K0/DE2 (3/4) Pin Name I/O SM11 Output Stepper motor 1 output sin + SM12 Stepper motor 1 output sin – SM13 Stepper motor 1 output cos + SM14 Stepper motor 1 output cos – SM21 ...
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Table 2-4. Non-port Pins for 78K0/DE2 (4/4) Pin Name I/O X1 Input Connecting resonator for high-speed system clock X2 – XT1 Input Connecting resonator for subsystem clock XT2 – ZPD14 Input Zero point detection input ZPD24 Remark Ext. (external reset): ...
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PD78F0838, 78F0839, 78F0840, 78F0841, 78F0842, 78F0843, 78F0846, 78F0847, 78F0848, 78F0849) <R> Pin Name I/O ANI0 to ANI7 Input AV – REF AV SS BUZ Output COM0 to COM3 Output Note CRxD Input Note CTxD Output EXCLK Input EXCLKS ...
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Table 2-5. Non-port Pins for 78K0/DF2 (2/4) Pin Name I/O RxD60 Input Serial data input to asynchronous serial interface <RxD60> RxD61 SCK10 I/O Clock input/output for serial interface SCK11 SCL0 I/O Clock input/output for tolerant/N-ch open-drain output ...
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Table 2-5. Non-port Pins for 78K0/DF2 (3/4) Pin Name I/O SEG26 Output LCD controller/driver segment signal outputs SEG27 Note3 SEG28 to SEG31 Note4 SEG32 to SEG39 SGO Output Sound generator output SGOA Sound generator amplitude PWM output SGOF Sound generator ...
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Table 2-5. Non-port Pins for 78K0/DF2 (4/4) Pin Name I/O SSI11 Input Serial interface chip select input TIO50 I/O External count clock input/timer output (TM50) TIO51 External count clock input/timer output (TM51) TIOP00 I/O External event count input/capture trigger input/external ...
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Description of Pin Functions 2.2.1 P00 to P07 (port 0) P00 to P07 function as an 8-bit I/O port. These pins also function as timer I/O and segment signal outputs for the LCD controller/driver. The following operation modes can ...
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P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for serial interface data I/O, clock I/O, timer I/O, external interrupt request input, and segment signal outputs for the ...
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P20 to P27 (port 2) P20 to P27 function as an 8-bit I/O port in 78K0/DF2 and P20 to P23 function as a 4-bit I/O port in 78K0/DE2. These pins also function as pins for A/D converter analog input. ...
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P60, P61 (port 6) P60 and P61 function as a 2-bit I/O port. P60 and P61 can be set to input port or output port in 1-bit units using port mode register 6 (PM6). P60 and P61 use of ...
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PCL This is a clock output pin. (e) BUZ This is a buzzer output pin. (f) RxD60 This is the serial data input pin of the asynchronous serial interface. (g) TxD60 This is the serial data output pin of ...
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P80 to P87 (port 8) P80 to P87 function as an 8-bit I/O port. These pins also function as stepper motor controller/driver outputs/inputs or LCD segment outputs. The following operation modes can be specified in 1-bit units. (1) Port ...
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P120 to P124 (port 12) P120 to P124 function as a 5-bit I/O port. These pins also function as external clock input for main system clock, external clock input for subsystem clock and potential input for external low-voltage detection. ...
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AV REF This is the A/D converter reference voltage input pin. When the A/D converter is not used, connect this pin directly to V 2.2. This is the A/D converter ground potential pin. Even when the A/D ...
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Pin I/O Circuits and Recommended Connection of Unused Pins The following table shows the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 Pin I/O Circuit List for the configuration of the ...
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PD78F0836, 78F0837, 78F0844, 78F0845) (2/2) Pin Name P60/SCL0/INTP1 <R> P61/SDA0/INTP3 Note 1 P70/CRxD /<RXD60/INTPR60> Note 1 P71/CTxD /<TxD60> P72/SGOA/PCL P73/SGO/SGOF/BUZ P80/SM11 to P82/SM13 P83/SM14/ZPD14 P84/SM21 to P86/SM23 P87/SM24/ZPD24 P120/EXLVI Note 2, 3 P121/X1/OCD0A Note 2 P122/X2/EXCLK/OCD0B Note ...
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Pin Name P00/SEG12/TIOP40 P01/SEG13/TIOP41 P02/SEG14/TIO50 P03/SEG15/TIO51 P04/SEG16/TIOP01 P05/SEG17/TIOP11 P06/SEG18/TIOP21 P07/SEG19/TIOP31 P10/SCK10/TxD61/INTP4 P11/SI10/RxD61/INTPR61 P12/SO10/INTP2 P13/SEG23/TIOP30/TxD60 P14/SEG22/TIOP20/RxD60/INTPR60 P15/SEG21/TIOP10 P16/SEG20/TIOP00 P17/INTP0/<TIOP30> Note 1 P20/ANI0 to P27/ANI7 P30/SEG4 Note 2, 3 P31/SEG5/OCD1A Note 2 P32/SEG6/OCD1B P33/SEG7 to P35/SEG9 P36/SEG10 P37/SEG11 P60/SCL0/INTP1 <R> P61/SDA0/INTP3 Notes ...
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Pin Name P70/<RXD60/INTPR60> P71/<TxD60> P72/SGOA/PCL P73/SGO/SGOF/BUZ P74/SCK11 P75/SI11 P76/SO11 P77/SSI11/<TIOP20> P80/SEG24 to P87/SEG31 P90/SEG32 to P93/SEG35 P94/SEG36 to P97/SEG39 P120/EXLVI Note 1, 2 P121/X1/OCD0A Note 1 P122/X2/EXCLK/OCD0B Note 1 P123/XT1 Note 1 P124/XT2/EXCLKS SEG0 to SEG3 COM0 to COM3 RESET ...
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PD78F0840, 78F0841, 78F0846, 78F0847) (1/2) Pin Name P00/SEG12/TIOP40 P01/SEG13/TIOP41 P02/SEG14/TIO50 P03/SEG15/TIO51 P04/SEG16/TIOP01 P05/SEG17/TIOP11 P06/SEG18/TIOP21 P07/SEG19/TIOP31 P10/SCK10/TxD61/INTP4 P11/SI10/RxD61/INTPR61 P12/SO10/INTP2 P13/SEG23/TIOP30/TxD60 P14/SEG22/TIOP20/RxD60/INTPR60 P15/SEG21/TIOP10 P16/SEG20/TIOP00 P17/INTP0/<TIOP30> Note 1 P20/ANI0 to P27/ANI7 P30/SEG4 Note 2, 3 P31/SEG5/OCD1A Note 2 P32/SEG6/OCD1B P33/SEG7 ...
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PD78F0840, 78F0841, 78F0846, 78F0847) (2/2) Pin Name Note 1 P70/CRxD /<RXD60/INTPR60> Note 1 P71/CTxD /<TxD60> P72/SGOA/PCL P73/SGO/SGOF/BUZ P74/SCK11 P75/SI11 P76/SO11 P77/SSI11/<TIOP20> P80/SEG24 to P87/SEG31 P90/SM31 to P92/SM33 P93/SM34/ZPD34 P94/SM41 to P96/SM43 P97/SM44/ZPD44 P120/EXLVI Note 2, 3 P121/X1/OCD0A ...
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PD78F0842, 78F0843, 78F0848, 78F0849) (1/2) Pin Name P00/SEG12/TIOP40 P01/SEG13/TIOP41 P02/SEG14/TIO50 P03/SEG15/TIO51 P04/SEG16/TIOP01 P05/SEG17/TIOP11 P06/SEG18/TIOP21 P07/SEG19/TIOP31 P10/SCK10/TxD61/INTP4 P11/SI10/RxD61/INTPR61 P12/SO10/INTP2 P13/SEG23/TIOP30/TxD60 P14/SEG22/TIOP20/RxD60/INTPR60 P15/SEG21/TIOP10 P16/SEG20/TIOP00 P17/INTP0/<TIOP30> Note 1 P20/ANI0 to P27/ANI7 P30/SEG4 Note 2, 3 P31/SEG5/OCD1A Note 2 P32/SEG6/OCD1B P33/SEG7 ...
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PD78F0842, 78F0843, 78F0848, 78F0849) (2/2) Pin Name Note 1 P70/CRxD /<RXD60/INTPR60> Note 1 P71/CTxD /<TxD60> P72/SGOA/PCL P73/SGO/SGOF/BUZ P74/SEG24/SCK11 P75/SEG25/SI11 P76/SEG26/SO11 P77/SEG27/SSI11/<TIOP20> P80/SM11 to P82/SM13 P83/SM14/ZPD14 P84/SM21 to P86/SM23 P87/SM24/ZPD24 P90/SM31 to P92/SM33 P93/SM34/ZPD34 P94/SM41 to P96/SM43 P97/SM44/ZPD44 ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-AG Pull-up enable V DD Data P-ch Output N-ch disable V SS Input enable CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/5) Type 5-AH Pull-up enable Data Output ...
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Type 5-AV ZPD Comparator + _ AV REF Data Output disable SMV Input enable Pull-down enable Type 5-AW Pull-up enable V Data Output disable V Input enable Pull-down enable 70 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List ...
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Type 17-U P-ch V LC0 P-ch V LC1 N-ch P-ch SEG data N-ch P-ch V LC2 N-ch N- Pull-down enable CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (3/5) Type 17-V Pull-up enable Data Output disable ...
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Type 17-W Pull-up enable Data Output disable Input enable Pull-down enable P-ch V LC0 P-ch V LC1 N-ch P-ch SEG data N-ch P-ch V LC2 N-ch N- CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List ...
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Type 18-G P-ch V LC0 P-ch V LC1 N-ch P-ch N-ch P-ch COM data P-ch V LC2 N-ch N- CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (5/5) Type 37-D Reset Data Output disable Input enable ...
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Memory Space Products in the 78K0/Dx2 can each access a 24, 32, 48 memory space. Figures 3-1 to 3-4 show the memory maps. Cautions 1. Regardless of the internal memory capacity, the initial values of the ...
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Figure 3-1. Memory Map ( PD78F0836, 78F0838, 78F0840, 78F0842 General-purpose Internal high-speed RAM F B ...
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Figure 3-2. Memory Map ( PD78F0844, 78F0846, 78F0848 Special function General-purpose Internal high-speed RAM F ...
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Figure 3-3. Memory Map ( PD78F0837, 78F0839, 78F0841, 78F0843 General-purpose Internal high-speed RAM F B ...
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Figure 3-4. Memory Map ( PD78F0845, 78F0847, 78F0849 Special function General-purpose Internal high-speed RAM F ...
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Remark The flash memory is divided into blocks (one block = 1 KB). For correspondence between the address values and block numbers in the flash memory, see the following table ...
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Internal program memory space The internal program memory space stores the program and table data. Normally addressed with the program counter (PC). 78K0/Dx2 products incorporate internal ROM (flash memory), as shown below. Part Number 78K0/DE2 PD78F0836 PD78F0838, ...
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CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area The option byte area is assigned to the 1-byte area of 0080H. Refer ...
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Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area FF00H to FFFFH (refer to Table 3-7. Special Function Register List). Caution Do not access addresses to which SFRs are not assigned. ...
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Figure 3-5. Correspondence between Data Memory and Addressing Special function registers (SFR) 256 General-purpose registers 32 8 bits ...
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Figure 3-6. Correspondence between Data Memory and Addressing ( PD78F0844, 78F0846, 78F0848 Special function registers (SFR) 256 General-purpose registers 32 8 bits ...
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Figure 3-7. Correspondence between Data Memory and Addressing Special function registers (SFR) 256 General-purpose registers 32 8 bits ...
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Figure 3-8. Correspondence between Data Memory and Addressing ( PD78F0845, 78F0847, 78F0849 Special function registers (SFR) 256 General-purpose registers 32 8 bits ...
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Processor Registers 78K0/Dx2 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a ...
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Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H SP FEDFH FEDEH FEDEH SP (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) FEE0H FEE0H SP ...
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Figure 3-13. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH (c) RETI, RETB instructions (when SP = FEDDH CHAPTER 3 CPU ARCHITECTURE FEE0H FEE0H FEDFH Register ...
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General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). ...
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Special Function Registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer and bit ...
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Table 3-7. Special Function Register List (1/6) Address Special Function Register (SFR) Name FF00H Port register 0 FF01H Port register 1 FF02H Port register 2 FF03H Port register 3 FF06H Port register 6 FF07H Port register 7 FF08H Port register ...
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Table 3-7. Special Function Register List (2/6) Address Special Function Register (SFR) Name FF2CH Port mode register 12 FF2DH A/D port configuration register FF2EH Asynchronous serial interface operation mode register 61 FF2FH Asynchronous serial interface reception error status register 61 ...
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Table 3-7. Special Function Register List (3/6) Address Special Function Register (SFR) Name FF50H Asynchronous serial interface operation mode register 60 FF53H Asynchronous serial interface reception error status register 60 FF54H Input noise filter control register 0 for 16-bit timer ...
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Table 3-7. Special Function Register List (4/6) Address Special Function Register (SFR) Name FF74H CAN module mask 2 register L FF75H FF76H CAN module mask 2 register H FF77H FF78H CAN module mask 3 register L FF79H FF7AH CAN module ...
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Table 3-7. Special Function Register List (5/6) Address Special Function Register (SFR) Name FFA0H Internal oscillator mode register FFA1H Main clock mode register FFA2H Main OSC control register FFA3H Oscillation stabilization time counter status register FFA4H Oscillation stabilization time select ...
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Address Special Function Register (SFR) Name <R> FFE0H Interrupt request flag register 0L FFE1H Interrupt request flag register 0H FFE2H Interrupt request flag register 1L FFE3H Interrupt request flag register 1H FFE4H Interrupt mask flag register 0L FFE5H Interrupt mask ...
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Address Extended Function Register (EFR) Name F980H 16-bit timer P0 control register 0 F981H 16-bit timer P0 control register 1 F982H 16-bit timer P0 I/O control register 0 F983H 16-bit timer P0 I/O control register 1 F984H 16-bit timer ...
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Address Extended Function Register (EFR) Name F9B0H 16-bit timer P3 control register 0 F9B1H 16-bit timer P3 control register 1 F9B2H 16-bit timer P3 I/O control register 0 F9B3H 16-bit timer P3 I/O control register 1 F9B4H 16-bit timer P3 ...
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Instruction Address Addressing An instruction address is determined by program counter (PC) contents and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. This ...
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Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration ...
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Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers ...
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Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes (Rn and RPn operation code. Register addressing is carried ...
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Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. [Operand format] [Description example] MOV A, !0FE00H; when setting !addr16 to FE00H Operation code [Illustration] 7 CHAPTER ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal RAM and special function ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
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Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing ...
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Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and ...
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Based indexed addressing [Function] The register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation ...
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Port Functions There are four types of pin I/O buffer power supplies: AV these power supplies and the pins is shown below. Power Supply P20 to P23, P24 to P27 AV REF EV Port pins other than P20 to ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-1. Port Types (1/2) (a) 78K0/DE2 P60 Port 6 P61 P70 Port 7 P73 P80 Port 8 P87 P120 Port 12 P124 Preliminary User’s Manual U19748EJ1V0UD P00 Port 0 P07 P10 Port 1 P17 P20 ...
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Port 6 Port 7 Port 8 Port 9 Port 12 116 CHAPTER 4 PORT FUNCTIONS Figure 4-1. Port Types (2/2) (b) 78K0/DF2 P00 P60 P61 P70 P07 P10 P77 P80 P17 P20 P87 P90 P27 P30 P97 P120 P124 P37 ...
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Port Configuration Ports include the following hardware. Item Control register Port mode register PM0 to PM3, PM6 to PM8, PM12 Port register P8, P12 Pull-up resistor PU0, PU1, PU3, PU6, PU7, PU12 option register ...
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Port 0 Port 8-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P07 ...
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Port 1 Port 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 ...
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WR PU PU1 PU11 Alternate function RD WR PORT P1 Output latch (P11 PM1 PM11 Note 78K0/DF2 only. P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR : ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P12 WR PU PU1 PU12 Alternate function RD WR PORT P1 Output latch (P12 PM1 PM12 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: ...
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WR PU PU1 PU13 Alternate function RD WR PORT P1 Output latch (P13 PM1 PM13 Alternate function (TMP3 output) Alternate function (UART60 output) LCD controller/driver WR PF LCDPFALL PF13 P1: Port register 1 PU1: Pull-up resistor option register ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P14 to P16 WR PU PU1 PU14 to PU16 Alternate function RD WR PORT P1 Output latch (P14 to P16 PM1 PM14 to PM16 Alternate function LCD controller/driver WR ...
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Port 2 Port 4-bit I/O port in 78K0/DE2 and an 8-bit I/O port in 78K0/DF2 with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port ...
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Figure 4-8. Block Diagram of P20 to P27 RD WR PORT P2 Output latch (P20 to P23, P24 to P27 Note ) WR PM PM2 PM20 to PM23, PM24 to PM27 Note A/D converter Note 78K0/DF2 only P2: Port register ...
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Port 3 Port 8-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When used as an input ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P30 and P33 PU3 PU30, PU33 to PU37 RD WR PORT P3 Output latch (P30, P33 to P37 PM3 PM30, PM33 to PM37 LCD controller/driver ...
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Figure 4-10. Block Diagram of P31 and P32 WR PU PU3 PU31, PU32 RD WR PORT P3 Output latch (P31, P32 PM3 PM31, PM32 LCD controller/driver WR PF LCDPF3 PF31, PF32 P3: Port register 3 PU3: Pull-up resistor ...
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Port 6 Port 2-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). P60 and P61 use of ...
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Port 7 Port 4-bit I/O port in 78K0/DE2 and an 8-bit I/O port in 78K0/DF2 with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port ...
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WR PU PU7 PU71 RD WR PORT P7 Output latch (P71 PM7 PM71 Alternate function Note PD78F0844, 78F0845, 78F0846, 78F0847, 78F0848, and 78F0849 only. P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register ...
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Figure 4-14. Block Diagram of P72 and P73 WR PU PU7 PU72, PU73 RD WR PORT P7 Output latch (P72, P73 PM7 PM72, PM73 Alternate function P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-15. Block Diagram of P74 (1/2) (a) PD78F038, 78F039, 78F040, 78F041, 78F036, and 78F047 WR PU PU7 PU74 Alternate function RD WR PORT P7 Output latch (P74 PM7 PM74 Alternate function P7: Port ...
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WR PU PU7 PU74 Alternate function RD WR PORT P7 Output latch (P74 PM7 PM74 Alternate function LCD controller/driver WR PF LCDPFALL PF7UPNIB P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-16. Block Diagram of P75 (1/2) (a) PD78F038, 78F039, 78F040, 78F041, 78F036, and 78F047 WR PU PU7 PU75 Alternate function RD WR PORT P7 Output latch (P75 PM7 PM75 P7: Port register 7 ...
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WR PU PU7 PU75 Alternate function RD WR PORT P7 Output latch (P75 PM7 PM75 LCD controller/driver WR PF LCDPFALL PF7UPNIB P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 LCDPFALL: ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P76 (1/2) (a) PD78F038, 78F039, 78F040, 78F041, 78F036, and 78F047 WR PU PU7 PU76 RD WR PORT P7 Output latch (P76 PM7 PM76 Alternate function P7: Port register 7 ...
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WR PU PU7 PU76 RD WR PORT P7 Output latch (P76 PM7 PM76 Alternate function LCD controller/driver WR PF LCDPFALL PF7UPNIB P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register 7 LCDPFALL: ...
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Figure 4-18. Block Diagram of P77 (1/2) (a) PD78F038, 78F039, 78F040, 78F041, 78F036, and 78F047 WR PU PU7 PU77 Alternate function RD WR PORT P7 Output latch (P77 PM7 PM77 Alternate function P7: Port register 7 PU7: Pull-up ...
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WR PU PU7 PU77 Alternate function RD WR PORT P7 Output latch (P77 PM7 PM77 Alternate function LCD controller/driver WR PF LCDPFALL PF7UPNIB P7: Port register 7 PU7: Pull-up resistor option register 7 PM7: Port mode register ...
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Port 8 Port 8-bit I/O port with an output latch. Port 8 can be set to the input mode or output mode in 1-bit units using port mode register 8 (PM8). This port can also be ...
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Figure 4-19. Block Diagram of P80 to P82 and P84 to P86 (2/2) (b) PD78F0838, 78F0839, 78F0840, 78F0841, 78F0846, and 78F0847 RD WR PORT P8 Output latch (P80 to P82, P84 to P86 PM8 PM80 to PM82, PM84 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P83 and P87 (1/2) (a) PD78F0836, 78F0837, 78F0842, 78F0843, 78F0844, 78F0845, 78F0848, and 78F0849 RD WR PORT P8 Output latch (P83, P87 PM8 PM83, PM87 Alternate function ZPD detect ...
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Figure 4-20. Block Diagram of P83 and P87 (2/2) (b) PD78F0838, 78F0839, 78F0840, 78F0841, 78F0846, and 78F0847 RD WR PORT P8 Output latch (P83, P87 PM8 PM83, PM87 LCD controller/driver WR PF LCDPFALL PF8ALL P8: Port register 8 ...
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Port 9 (78K0/DF2 only) Port 8-bit I/O port with an output latch. Port 9 can be set to the input mode or output mode in 1-bit units using port mode register 9 (PM9). This port can ...
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Figure 4-21. Block Diagram of P90 to P92 and P94 to P96 (2/2) (b) PD78F0840, 78F0841, 78F0842, 78F0843, 78F0846, 78F0847, 78F0848, and 78F0849 RD WR PORT P9 Output latch (P90 to P92, P94 to P96 PM9 PM90 to ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-22. Block Diagram of P93 and P97 (1/2) ( PORT P9 Output latch (P93, P97 PM9 PM93, PM97 LCD controller/driver WR PF LCDPFALL PF9ALL P9: Port register 9 PM9: Port mode ...
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Figure 4-22. Block Diagram of P93 and P97 (2/2) (b) PD78F0840, 78F0841, 78F0842, 78F0843, 78F0846, 78F0847, 78F0848, and 78F0849 RD WR PORT P9 Output latch (P93, P97 PM9 PM93, PM97 Alternate function ZPD detect input P9: Port register ...
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Port 12 Port 5-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input ...
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WR PU PU12 PU120 Alternate function RD WR PORT P12 Output latch (P120 PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WR : Write signal 150 ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P121 to P124 OSCSEL, OSCSELS RD WR PORT P12 Output latch (P122, P124 PM12 PM122, PM124 OSCCTL OSCSEL, OSCSELS RD WR PORT P12 Output latch (P121, P123 ...
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Registers Controlling Port Function Port functions are controlled by the following four types of registers. Port mode registers (PM0 to PM3, PM3 to PM8, PM9 Port registers ( P8, P9 Pull-up resistor option registers (PU0, ...
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Port mode registers (PM0 to PM3, PM6 to PM9, PM12) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation ...
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Figure 4-25. Format of Port Mode Register (2/2) Symbol Note PM9 PM97 PM96 PM95 PM12 PMmn 0 1 Note 78K0/DF2 only 154 CHAPTER 4 PORT FUNCTIONS PM94 ...
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Port registers ( P9, P12) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level ...
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Figure 4-26. Format of Port Register (2/2) Symbol Note P9 P97 P96 P95 P12 Remarks 1. An undefined value (pin input level) is read for the value after reset when P0 ...
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Pull-up resistor option registers (PU0, PU1, PU3, PU6, PU7, PU12) These registers specify whether the on-chip pull-up resistors of P00 to P07, P10 to P17, P30 to P37, P60, P61, P70 to P77, and P120 are to be used ...
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Port output mode control register 6 (POM6) This register sets the output mode of P60 and P61 in 1-bit units. During I and P61/SDA0/INTP3 to N-ch open-drain output (5 V-torelant) mode. This register can be set by a 1-bit ...
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LCD port function register 3 (LCDPF3) This register sets whether to use pins P30 to P37 as port pins (other than segment output pins) or segment output pins. LCDPF3 is set using a 1-bit or 8-bit memory manipulation instruction. ...
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Stepper motor port mode control register (SMPC) This register sets the output mode of stepper motor controller/driver. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure ...
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A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7 (P20/ANI0 to P23/ANI3 in 78K0/DE2, P20/ANI0 to P27/ANI7 in 78K0/DF2) pins to analog input of A/D converter or digital I/O of port. ADPC can be set by ...
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Settings of LCDPFALL, LCDPF0, LCDPF3, SMPC, ISC, Port Mode Register, and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the LCDPFALL, LCDPF0, LCDPF3, SMPC, ISC, port mode register, and output latch ...
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Table 4-4. Settings of LCDPFALL, LCDPF0, LCDPF3, SMPC, ISC, Port Mode Register, and Output Latch <R> Pin Name Alternate Function Function Name P00 SEG12 TIOP40 <R> SEG13 P01 TIOP41 SEG14 P02 TIO50 SEG15 P03 TIO51 SEG16 P04 TIOP01 SEG17 P05 ...
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Table 4-4. Settings of LCDPFALL, LCDPF0, LCDPF3, SMPC, ISC, Port Mode Register, and Output Latch Pin Name Alternate Function Function Name P14 INTPR60 RxD60 SEG22 <R> TIOP20 SEG21 P15 TIOP10 SEG20 P16 TIOP00 INTP0 P17 <TIOP30> ANI0 to ANI3 P20 ...
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Table 4-4. Settings of LCDPFALL, LCDPF0, LCDPF3, SMPC, ISC, Port Mode Register, and Output Latch Pin Name Alternate Function Function Name I/O P72 PCL Output SGOA Output BUZ P73 Output SGO Output SGOF Output SM11 to SM13 P80 to P82 ...
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Table 4-4. Settings of LCDPFALL, LCDPF0, LCDPF3, SMPC, ISC, Port Mode Register, and Output Latch Pin Name Alternate Function Function Name SEG12 P00 TIOP40 <R> SEG13 P01 TIOP41 SEG14 P02 TIO50 SEG15 P03 TIO51 SEG16 P04 TIOP01 SEG17 P05 TIOP11 ...
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Table 4-4. Settings of LCDPFALL, LCDPF0, LCDPF3, SMPC, ISC, Port Mode Register, and Output Latch Pin Name Alternate Function Function Name INTPR60 P14 RxD60 SEG22 TIOP20 <R> P15 SEG21 TIOP10 SEG20 P16 TIOP00 INTP0 P17 <TIOP30> <R> ANI0 to ANI7 ...
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Table 4-4. Settings of LCDPFALL, LCDPF0, LCDPF3, SMPC, ISC, Port Mode Register, and Output Latch Pin Name Alternate Function Function Name I/O SCK11 Input P74 Output Note1 SEG24 Output SI11 P75 Input Note1 SEG25 Output P76 SO11 Output Note1 SEG26 ...
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Table 4-4. Settings of LCDPFALL, LCDPF0, LCDPF3, SMPC, ISC, Port Mode Register, and Output Latch Pin Name Alternate Function Function Name I/O SEG36 to P94 to P96 Output Note1 SEG38 Note2 SM41 to SM43 Output Note1 SEG39 P97 Output Note2 ...
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Remarks 1. The function of the ANI0/P20 to ANI7/P27 pins can be selected by using the A/D port configuration register (ADPC), the analog input channel specification register (ADS), and PM2. ADPC Digital I/O selection Input mode Output mode Analog input ...
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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.5.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, ...
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Cautions on 1-bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject ...
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Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a ...
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Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Control registers Processor clock control register (PCC) Internal oscillator mode register (RCM) Main clock mode register (MCM) Main OSC control register ...
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CHAPTER 5 CLOCK GENERATOR Selector Preliminary User’s Manual U19748EJ1V0UD 175 ...
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Remark clock oscillation frequency Internal high-speed oscillation clock frequency OSC8 f : External main system clock frequency EXT f : High-speed system clock oscillation frequency Main system clock oscillation frequency MAIN ...
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Processor clock control register (PCC) This register is used to select the CPU clock and the division ratio. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC to 01H. Figure 5-2. Format ...
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Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock (f ) CPU High-Speed System Clock At 10 MHz Operation 0 MAIN 0 MAIN 2 0 MAIN 3 1.6 ...
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Internal oscillator mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H Figure 5-3. Format of Internal ...
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Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears ...
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Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU ...
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Clock operation mode select register (OSCCTL) This register selects the operation modes of the high-speed system and subsystem clocks. OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. ...
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CHAPTER 5 CLOCK GENERATOR Cautions 6. To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP) of the main OSC control register (MOC (the X1 oscillator stops or the external clock from ...
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Oscillation stabilization time counter status register (OSTC) This is the status register of the X1 clock oscillation stabilization time counter. oscillation clock or subsystem clock is used as the CPU clock, the X1 clock oscillation stabilization time can be ...
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Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. The wait time set by OSTS is valid only after the STOP mode is ...
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System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator ( MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input ...
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Caution When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-9 and 5-10 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as ...
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Figure 5-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, ...
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When subsystem clock is not used not necessary to use the subsystem clock for low power consumption operations not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to ...
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Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode. Main system clock f MAIN High-speed system clock clock f X External main system ...
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Improvement of performance Because the CPU can be started without waiting for the X1 clock oscillation stabilization time, the total performance can be improved. A timing diagram of the CPU default start using the internal high-speed oscillation clock is ...
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Cautions 1. When the standup of voltage until it reaches 1.8 V from the time of a power supply injection is looser than 0.5 V/ms (MIN.), input a low level into RESET pin, or set up 2.7 V/1.59 V POC ...
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The internal reset signal by the power-on clear (POC) circuit is generated after a power supply injection. <2> If power supply voltage exceeds 1.59 V (TYP.), reset will be canceled and the oscillation start of the high- speed oscillator ...
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Controlling Clock 5.6.1 Controlling high-speed system clock The following two types of high-speed system clocks are available. X1 clock: Crystal/ceramic resonator is connected across the X1 and X2 pins. External main system clock: External clock is input to the ...
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Example of setting procedure when oscillating the X1 clock <1> Setting frequency (OSCCTL register) Using AMPH, set the gain of the on-chip oscillator according to the frequency to be used. Note AMPH 4 MHz f 10 MHz 0 IN ...
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Example of setting procedure when using the external main system clock <1> Setting frequency (OSCCTL register) Using AMPH, set the frequency to be used. Note AMPH 4 MHz MHz < Note Set ...
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Example of setting procedure when using high-speed system clock as CPU clock and peripheral hardware clock <1> Setting high-speed system clock oscillation (See 5.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting ...
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Example of setting procedure when stopping the high-speed system clock The high-speed system clock can be stopped in the following two ways. Executing the STOP instruction and stopping the X1 oscillation (disabling clock input if the external clock is ...