UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 781

• Manufacturer Part Number: UPD78F0838
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(2) In 2.7 V / 1.59V POC mode (option byte: LVISTART = 1)
oscillation clock (f
(when X1 oscillation
Internal reset signal
Internal high-speed
Notes 1.
Cautions 1. Set the low-voltage detector by software after the reset status is released (see CHAPTER 24
Remark V
system clock (f
V
V
Supply voltage
DDPOC
POC
High-speed
is selected)
= 1.59 V (TYP.)
= 2.7 V (TYP.)
1.8 V
2.
CPU
OSC8
(V
Note 1
V
IN
Figure 23-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
V
DD
0 V
2. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
LVI
)
)
The guaranteed operation range for the (A) grade products is 1.8 V
5.5 V for the (A2) grade products. To set the voltage range below the guaranteed operation range to
the reset state when the supply voltage falls, use the reset function of the low-voltage detector, or input
a low level to the RESET pin.
The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
LVI
POC
)
Operation
LOW-VOLTAGE DETECTOR).
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93
ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated
before reset processing.
stops
: LVI detection voltage
: POC detection voltage
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
Set LVI to be
used for reset
oscillation clock)
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
Preliminary User’s Manual U19748EJ1V0UD
and Low-Voltage Detector (2/2)
Note 2
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
used for interrupt
Set LVI to be
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
Note 2
Reset period
(oscillation
stop)
Wait for oscillation
accuracy stabilization
(86 to 361 s)
Reset processing (11 to 45 s)
Set LVI to be
used for reset
V
DD
oscillation clock)
(internal high-speed
Normal operation
specified by software.
Starting oscillation is
5.5 V, and 2.7 V
Note 2
Operation stops
V
DD
779