UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 717

• Manufacturer Part Number: UPD78F0838
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(2) SG0 frequency low register (SG0FL)
(3) SG0 frequency high register (SG0FH)
Remarks 1. The bits SG0FL[15:9] are not used.
Remarks 1. The bits SG0FH[15:6] are not used.
The 16-bit SG0FL register is used to specify the target value for the PWM frequency. It holds the target value for
the 9-bit counter SG0FL.
This register can be read/written in 16-bit units. It cannot be written if bit SG0CTL.PWR = 0.
This register is cleared by any reset.
For the calculation of the resulting PWM frequency refer to 18.3.2 (2) PWM calculations.
The value written to SG0FL defines also the reference value for the maximum sound amplitude (100% PWM duty
cycle). A 100 % duty cycle (continually high) will be generated if the SG0PWM value is higher than the SG0FL
value. For details see 18.3.2 (2) PWM calculations.
The 16-bit SG0FH register is used to specify the final tone frequency. It holds the target value for the 6-bit counter
SG0FH.
This register can be read/written in 16-bit units. It cannot be written if bit SG0CTL.PWR = 0.
This register is cleared by any reset.
For the calculation of the resulting tone frequency refer to 18.3.1 (2) Tone frequency calculation.
Address: FFA8H
Address: FFAAH
Symbol
Symbol
SG0FH
SG0FL
2. The maximum value to be written is 510 (01FEH). This yields a PWM frequency of 19.7 kHz in case
3. The value read from this register does not necessarily reflect the current PWM frequency, because
2. Legal values depend on the contents of register SG0FL which defines the frequency of the input
3. The value read from this register does not necessarily reflect the current tone frequency, because this
of the sound generator input clock SG0CLK 10 MHz. The minimum value to be written depends on
the capability of the external circuit. A value of 255 (00FFH) would yield a PWM frequency of 39.1
kHz in case of the sound generator input clock SG0CLK 10 MHz.
this frequency is determined by the frequency compare buffer value. The buffer might not be updated
yet.
For details see 18.3.1 (1) Updating the frequency buffer values.
pulse. For example: If the counter SG0FL generates a frequency of 32.4 kHz, a value of 63 would
generate a tone frequency of 253 Hz.
frequency is determined by the frequency compare buffer value. The buffer might not be updated yet.
For details see 18.3.1 (1) Updating the frequency buffer values.
15
15
0
0
After reset: 0000H
After reset: 0000H
14
14
0
0
13
13
0
0
12
12
0
0
CHAPTER 18 SOUND GENERATOR
Preliminary User’s Manual U19748EJ1V0UD
11
11
0
0
R/W
R/W
10
10
0
0
9
0
9
0
8
8
0
7
7
0
6
Counter SG0FL target value
6
0
5
5
Counter SG0FH target value
4
4
3
3
2
2
1
1
0
0
715