UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 387

• Manufacturer Part Number: UPD78F0838
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

<R>
<R>
Cautions 1.
Note If “reception as 0 parity” is selected, the parity is not judged.
Figure 12-8. Format of Asynchronous Serial Interface Operation Mode Register 61 (ASIM61) (2/2)
PS611
CL61
SL61
0
0
1
1
0
1
0
1
2.
3.
4.
5.
6.
7.
8.
9.
asynchronous serial interface reception error status register 61 (ASIS61) is not set and the error
interrupt does not occur.
Be sure to set bit 0 to 1.
To start the transmission, set POWER61 to 1 and then set TXE61 to 1. To stop the
transmission, clear TXE61 to 0, and then clear POWER61 to 0.
To start the reception, set POWER61 to 1 and then set RXE61 to 1. To stop the reception,
clear RXE61 to 0, and then clear POWER61 to 0.
Set POWER61 to 1 and then set RXE61 to 1 while a high level is input to the RxD61 pins. If
POWER61 is set to 1 and RXE61 is set to 1 while a low level is input, reception is started.
TXE61 and RXE61 are synchronized by the base clock (f
transmission or reception again, set TXE61 or RXE61 to 1 at least two clocks of the base
clock after TXE61 or RXE61 has been cleared to 0. If TXE61 or RXE61 is set within two clocks
of the base clock, the transmission circuit or reception circuit may not be initialized.
Set transmit data to TXB61 at least one base clock (f
Clear the TXE61 and RXE61 bits to 0 before rewriting the PS611, PS601, and CL61 bits.
Fix the PS611 and PS601 bits to 0 when used in LIN communication operation.
Clear TXE61 to 0 before rewriting the SL61 bit. Reception is always performed with “the
number of stop bits = 1”, and therefore, is not affected by the set value of the SL61 bit.
Character length of data = 7 bits
Character length of data = 8 bits
Number of stop bits = 1
Number of stop bits = 2
PS601
0
1
0
1
CHAPTER 12 SERIAL INTERFACES UART60 AND UART61
Does not output parity bit.
Outputs 0 parity.
Outputs odd parity.
Outputs even parity.
Preliminary User’s Manual U19748EJ1V0UD
Transmission operation
Specifies character length of transmit/receive data
Specifies number of stop bits of transmit data
Reception without parity
Reception as 0 parity
Judges as odd parity.
Judges as even parity.
XCLK6
) after setting TXE61 = 1.
XCLK6
Reception operation
Therefore, bit 2 (PE61) of
) set by CKSR61. To enable
Note
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