UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 457

• Manufacturer Part Number: UPD78F0838
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(2) Slave address register 0 (SVA0)
(3) SO latch
(4) Wake-up controller
(5) Prescaler
(6) Serial clock counter
(7) Interrupt request signal generator
(8) Serial clock controller
(9) Serial clock wait controller
(10) ACK generator, stop condition detector, start condition detector, and ACK detector
(11) Data hold time correction circuit
This register stores local addresses when in slave mode.
SVA0 is set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected).
Reset signal generation clears SVA0 to 00H.
Note Bit 0 is fixed to 0.
The SO latch is used to retain the SDA0 pin’s output level.
This circuit generates an interrupt request (INTIIC0) when the address received by this register matches the
address value set to slave address register 0 (SVA0) or when an extension code is received.
This selects the sampling clock to be used.
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to
verify that 8-bit data was transmitted or received.
This circuit controls the generation of interrupt request signals (INTIIC0).
An I
• Falling edge of eighth or ninth clock of the serial clock (set by WTIM0 bit)
• Interrupt request generated when a stop condition is detected (set by SPIE0 bit)
Remark
In master mode, this circuit generates the clock output via the SCL0 pin from a sampling clock.
This circuit controls the wait timing.
These circuits generate and detect each status.
This circuit generates the hold time for data corresponding to the falling edge of the serial clock.
2
C interrupt request is generated by the following two triggers.
Address: FFB2H
Symbol
SVA0
WTIM0 bit: Bit 3 of IIC control register 0 (IICC0)
SPIE0 bit: Bit 4 of IIC control register 0 (IICC0)
Figure 14-4. Format of Slave Address Register 0 (SVA0)
7
After reset: 00H
CHAPTER 14 SERIAL INTERFACE IIC0
6
Preliminary User’s Manual U19748EJ1V0UD
5
R/W
4
3
2
1
0
Note
0
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