UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 714

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UPD78F0838

Manufacturer Part Number
UPD78F0838
Description
8-bit Single-chip Microcontrollers
Manufacturer
Renesas Electronics Corporation.
Datasheet
clock oscillation frequency f
Tone generator
registers are automatically copied to compare buffers. The counters are reset to zero when their values match the
contents of the associated compare buffers.
the PWM frequency.
frequency between 250 Hz and 6 kHz and a 50 % duty cycle.
PWM
SG0PWM. The value written to this register is automatically copied to the associated volume compare buffer.
counter value matches the contents of the volume buffer. Thus, the PWM output signal can have a duty cycle between
0 % (null volume) and 100 % (maximum volume).
Outputs
SG0OF and pin SGOA the PWM signal SG0OA that holds the volume (“amplitude”) information.
712
The Sound Generator's input clock frequency f
The tone generator consists of two up-counters with compare registers. The values written to the frequency
The 9-bit counter SG0FL generates a clock with a frequency between 32 kHz and 64 kHz. This clock constitutes
It is also the input of the second 6-bit counter SG0FH. The resulting tone signal behind the by-two-divider has a
The PWM modulates the duty cycle according to the desired volume. It is controlled by the volume register
The PWM continually compares the value of the counter SG0FL with the contents of its volume compare buffer.
The RS flipflop of the PWM is set by the pulses generated by the counter SG0FL. It is reset when the SG0FL
The PWM frequency is above 32 kHz and hence outside the audible range.
The Sound Generator is connected to the pins SGO and SGOA. By default, pin SGO provides the tone signal
If bit SG0CTL.OS is set, pin SGO provides the composite signal SG0O that can directly control a speaker circuit.
PRS
in two.
CHAPTER 18 SOUND GENERATOR
Preliminary User’s Manual U19748EJ1V0UD
SG0CLK
is the 10 MHz clock which is divided the peripheral hardware

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