UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 481

• Manufacturer Part Number: UPD78F0838
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

14.5.7 Canceling wait
resumed.
register 0 (IICC0) to 1.
output to SDA0 because the timing for changing the SDA0 line conflicts with the timing for writing IIC0.
so that the wait state can be canceled.
IICC0, so that the wait state can be canceled.
14.5.8 Interrupt request (INTIIC0) generation timing and wait control
and the corresponding wait control, as shown in Table 14-3.
The I
When the above wait canceling processing is executed, the I
To cancel a wait state and transmit data (including addresses), write the data to IIC0.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IIC0 control
To generate a restart condition after canceling a wait state, set bit 1 (STT0) of IICC0 to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of IICC0 to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to IIC0 after canceling a wait state by setting WREL0 to 1, an incorrect value may be
In addition to the above, communication is stopped if IICE0 is cleared to 0 when communication has been aborted,
If the I
The setting of bit 3 (WTIM0) of IIC control register 0 (IICC0) determines the timing by which INTIIC0 is generated
WTIM0
Notes 1. The slave device’s INTIIC0 signal and wait period occurs at the falling edge of the ninth clock only when
Remark
Writing data to IIC shift register 0 (IIC0)
Setting bit 5 (WREL0) of IIC control register 0 (IICC0) (canceling wait)
Setting bit 1 (STT0) of IIC0 register (generating start condition)
Setting bit 0 (SPT0) of IIC0 register (generating stop condition)
Note Master only
0
1
2
C usually cancels a wait state by the following processing.
2
2. If the received address does not match the contents of slave address register 0 (SVA0) and extension
C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of
there is a match with the address set to slave address register 0 (SVA0).
At this point, ACK is generated regardless of the value set to IICC0’s bit 2 (ACKE0). For a slave device
that has received an extension code, INTIIC0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIIC0 is generated at the falling edge of the 9th
clock, but wait does not occur.
code is not received, neither INTIIC0 nor a wait occurs.
The numbers in the table indicate the number of the serial clock’s clock signals. Interrupt requests and
wait control are both synchronized with the falling edge of these clock signals.
Address
9
9
Notes 1, 2
Notes 1, 2
During Slave Device Operation
Table 14-3. INTIIC0 Generation Timing and Wait Control
Data Reception
8
9
Note 2
Note 2
CHAPTER 14 SERIAL INTERFACE IIC0
Preliminary User’s Manual U19748EJ1V0UD
Data Transmission
8
9
Note 2
Note 2
Note
Note
2
C cancels the wait state and communication is
Address
9
9
During Master Device Operation
Data Reception
8
9
Data Transmission
8
9
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