UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 273

• Manufacturer Part Number: UPD78F0838
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TIOPn1 pin.
After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a
trigger is generated again while the one-shot pulse is being output, it is ignored.
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTPnCC1
is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
trigger.
When the TPnCE bit is set to 1, 16-bit timer/event counter P waits for a trigger. When the trigger is generated, the
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal INTTPnCC0 is generated when the 16-bit counter counts after its
The valid edge of an external trigger input or setting the software trigger (TPnCTL1.TPnEST bit) to 1 is used as the
Remark
External trigger input
(only when software
INTTPnCC0 signal
INTTPnCC1 signal
(TIOPn0 pin input)
TPnCCR0 register
TIOPn0 pin output
TPnCCR1 register
TIOPn1 pin output
Output delay period = (Set value of TPnCCR1 register)
Active level width = (Set value of TPnCCR0 register
trigger is used)
16-bit counter
TPnCE bit
n = 0 to 4
m = 0, 1
FFFFH
0000H
Figure 6-24. Basic Timing in One-shot Pulse Output Mode
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Delay
(D
D
1
1
)
Preliminary User’s Manual U19748EJ1V0UD
Active
level width
(D
D
0
0
D
1
+ 1)
Set value of TPnCCR1 register + 1)
Delay
(D
D
Count clock cycle
1
1
)
Active
level width
(D
D
D
D
0
0
0
1
D
1
+ 1)
Delay
(D
D
1
1
)
Active
level width
(D
D
0
0
D
1
+ 1)
Count clock cycle
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