UPD78F0838 Renesas Electronics Corporation., UPD78F0838 Datasheet - Page 675

• Manufacturer Part Number: UPD78F0838
• Description: 8-bit Single-chip Microcontrollers
• Manufacturer: Renesas Electronics Corporation.

(5) Compare control registers (MCMPCk) (k = 1 to 4)
Note This bit may be written, but writing is ignored.
The 8-bit MCMPCk registers control the operation of the corresponding compare registers and the output
direction of the PWM pin.
These registers can be read/written in 8-bit or 1-bit units.
This register is cleared by any reset.
Address: F9CAH, F9CCH, F9CEH, F9F8H
Symbol
MCMPCk
Remark This bit functions as a control bit and status flag. It is automatically reset to zero upon the next timer
AOUT
TWIN
ADB1
ADB0
ZPD
TEN
0
1
0
1
0
1
0
1
0
1
0
1
AOUT
7
Figure 16-3. Format of Compare Control Registers (MCMPCk) (1/2)
counter overflow.
The PWM signals for sine and cosine side are output to those pins that are selected by bits DIR0 and
DIR1. At all other pins, the output signal is 0 (SMV
The PWM signal for the sine side is output to pins SMk1 and SMk2. The PWM signal for the cosine
side is output to pins SMk3 and SMk4.
Disable writing to ZPD bit from the comparator (No 0-point detection)
Enable writing to ZPD bit from the comparator (0-point detection)
No induced voltage detection (0-point detection)
Induced voltage detection (No 0-point detection)
MCMPk0/MCMPk1 master-to-slave register copy is disabled. New data can be written to compare
registers MCMPk0 or MCMPk1.
MCMPk0/MCMPk1 master-to-slave register copy is enabled. The copy process will take place when
CNT0 overflows. Don't write to compare registers MCMPk0 or MCMPk1 while MCMPCk.TEN = 1.
No 1-bit addition to PWM signal
1-bit addition to PWM signal
No 1-bit addition to PWM signal
1-bit addition to PWM signal
CHAPTER 16 STEPPER MOTOR CONTROLLER/DRIVER
TWIN
6
Preliminary User’s Manual U19748EJ1V0UD
ZPD
Induced voltage detection bit for 0-point detection (Read only)
5
After reset: 00H
Note
Output pins for sine and cosine signals
1-bit addition function for cosine side
TEN
1-bit addition function for sine side
0-point detection timing window
4
Transfer enable control bit
R/W
ADB1
3
SS
level).
ADB0
2
DIR1
1
DIR0
0
673