XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 96

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Functional Description
Slave Parallel Mode
For additional information, refer to the “Slave Parallel
(SelectMAP) Mode” chapter in UG332.
In Slave Parallel mode (M[2:0] = <1:1:0>), an external host,
such as a microprocessor or microcontroller, writes
byte-wide configuration data into the FPGA, using a typical
peripheral interface as shown in
The external download host starts the configuration process
by pulsing PROG_B and monitoring that the INIT_B pin
goes High, indicating that the FPGA is ready to receive its
first data. The host asserts the active-Low chip-select signal
(CSI_B) and the active-Low Write signal (RDWR_B). The
host then continues supplying data and clock signals until
either the FPGA’s DONE pin goes High, indicating a suc-
cessful configuration, or until the FPGA’s INIT_B pin goes
Low, indicating a configuration error.
96
- Internal memory
- Disk drive
- Over network
- Over RF link
Configuration
Memory
Source
Download Host
Intelligent
Recommend
open-drain
PROG_B
- Microcontroller
- Processor
- Tester
- Computer
driver
READ/WRITE
Figure
VCC
GND
PROG_B
SELECT
V
CLOCK
INIT_B
TMS
TDO
Figure 61: Slave Parallel Configuration Mode
TCK
DONE
BUSY
D[7:0]
TDI
61.
+2.5V
JTAG
www.xilinx.com
Parallel
Slave
Mode
‘1’
‘1’
‘0’
P
The FPGA captures data on the rising CCLK edge. If the
CCLK frequency exceeds 50 MHz, then the host must also
monitor the FPGA’s BUSY output. If the FPGA asserts
BUSY High, the host must hold the data for an additional
clock cycle, until BUSY returns Low. If the CCLK frequency
is 50 MHz or below, the BUSY pin may be ignored but
actively drives during configuration.
The configuration process requires more clock cycles than
indicated from the configuration file size. Additional clocks
are required during the FPGA’s start-up sequence, espe-
cially if the FPGA is programmed to wait for selected Digital
Clock Managers (DCMs) to lock to their respective clock
inputs (see
If the Slave Parallel interface is only used to configure the
FPGA, never to read data back, then the RDWR_B signal
can also be eliminated from the interface. However,
RDWR_B must remain Low during configuration.
HSWAP
M2
M1
M0
D[7:0]
BUSY
CSI_B
RDWR_B
CCLK
TDI
TMS
TCK
PROG_B
Spartan-3E
Start-Up, page
VCCINT
+1.2V
GND
FPGA
VCCAUX
VCCO_0
VCCO_2
CSO_B
INIT_B
DONE
TDO
108).
VCCO_0
DS312-2 (v3.6) May 29, 2007
+2.5V
V
Product Specification
V
DS312-2_52_103105
+2.5V
R