XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 69

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 43: Spartan-3E Configuration Mode Options and Pin Settings
Configuration Bitstream Image Sizes
A specific Spartan-3E part type always requires a constant
number of configuration bits, regardless of design complex-
ity, as shown in
multiple-FPGA daisy-chain design roughly equals the sum
of the individual file sizes.
Table 44: Number of Bits to Program a Spartan-3E
FPGA (Uncompressed Bitstreams)
Pin Behavior During Configuration
or additional information, refer to the “Configuration Pins
and Behavior during Configuration” chapter in UG332.
Table 45: Pin Behavior during Configuration
DS312-2 (v3.6) May 29, 2007
Product Specification
Uses low-cost,
industry-standard
Flash
Supports optional
MultiBoot,
multi-configuration
mode
IP* (input-only)
IO* (user-I/O)
Spartan-3E FPGA
Pin Name
PROG_B
HSWAP
DONE
CCLK
XC3S1200E
XC3S1600E
TMS
TDO
TCK
TDI
XC3S100E
XC3S250E
XC3S500E
M2
M1
M0
R
Table
Master Serial
CCLK (I/O)
PROG_B
HSWAP
44. The configuration file size for a
DONE
TMS
TDO
TCK
TDI
0
0
0
Master
Serial
Configuration Bits
SPI (Serial
CCLK (I/O)
PROG_B
Number of
HSWAP
1,353,728
2,270,208
3,841,184
5,969,696
Flash)
DONE
581,344
TMS
TDO
TCK
TDI
0
0
1
SPI
BPI (Parallel
NOR Flash)
CCLK (I/O)
PROG_B
1 = Down
HSWAP
DONE
0 = Up
www.xilinx.com
TMS
TDO
TCK
TDI
0
1
BPI
Table 45
configuration process. The actual behavior depends on the
values applied to the M2, M1, and M0 mode select pins and
the HSWAP pin. The mode select pins determine which of
the I/O pins are borrowed during configuration and how they
function. In JTAG configuration mode, no user-I/O pins are
borrowed for configuration.
All user-I/O pins, input-only pins, and dual-purpose pins that
are not actively involved in the currently-select configuration
mode are high impedance (floating, three-stated, Hi-Z) dur-
ing the configuration process. These pins are indicated in
Table 45
The HSWAP input controls whether all user-I/O pins,
input-only pins, and dual-purpose pins have a pull-up resis-
tor to the supply rail or not. When HSWAP is Low, each pin
has an internal pull-up resistor that is active throughout con-
figuration. After configuration, pull-up and pull-down resis-
tors are available in the FPGA application as described in
Pull-Up and Pull-Down
The yellow-shaded table entries or cells represent pins
where the pull-up resistor is always enabled during configu-
ration, regardless of the HSWAP input. The post-configura-
tion behavior of these pins is defined by Bitstream
Generator options as defined in
PROG_B
HSWAP
DONE
JTAG
TMS
TDO
TCK
TDI
1
0
1
as gray shaded table entries or cells.
shows how various pins behave during the FPGA
Slave Parallel
PROG_B
CCLK (I)
Parallel
HSWAP
DONE
Slave
TMS
TDO
TCK
TDI
1
1
0
Resistors.
Slave Serial
Slave Serial
Table
PROG_B
CCLK (I)
HSWAP
Functional Description
DONE
TMS
TCK
TDO
TDI
1
1
1
68.
I/O Bank
JTAG
Supply/
V
V
V
V
V
V
CCAUX
CCAUX
CCAUX
CCAUX
CCAUX
CCAUX
0
2
2
2
2
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