XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 21

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

are pulled down (PULLDOWN). The designer can control
how the unused I/Os are terminated after GTS is released
by setting the Bitstream Generator (BitGen) option Unused-
Pin to PULLUP, PULLDOWN, or FLOAT.
One clock cycle later (default), the Global Write Enable
(GWE) net is released allowing the RAM and registers to
change states. Once in User mode, any pull-up resistors
enabled by HSWAP revert to the user settings and HSWAP
is available as a general-purpose I/O. For more information
on PULLUP and PULLDOWN, see
Resistors.
DS312-2 (v3.6) May 29, 2007
Product Specification
R
Pull-Up and Pull-Down
www.xilinx.com
Behavior of Unused I/O Pins After
Configuration
By default, the Xilinx ISE development software automati-
cally configures all unused I/O pins as input pins with indi-
vidual internal pull-down resistors to GND.
This default behavior is controlled by the UnusedPin bit-
stream generator (BitGen) option, as described in
JTAG Boundary-Scan Capability
All Spartan-3E IOBs support boundary-scan testing com-
patible with IEEE 1149.1/1532 standards. During bound-
ary-scan operations such as EXTEST and HIGHZ the
pull-down resistor is active. See
mation on programming via JTAG.
JTAG Mode
Functional Description
for more infor-
Table
68.
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