XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 12

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Functional Description
Input Delay Functions
Each IOB has a programmable delay block that optionally
delays the input signal. In
delayed by an initial delay element. The initial delay then
feeds a 7-tap delay line. The initial and tap delays vary; refer
to timing reports for specific delay values. All seven taps are
available via a multiplexer for use as an asynchronous input
directly into the FPGA fabric. In this way, the delay is pro-
grammable in 14 steps. Three of the seven taps are also
available via a multiplexer to the D inputs of the synchro-
nous storage elements. The delay inserted in the path to the
storage element can be varied in six steps. The first, coarse
delay element is common to both asynchronous and syn-
chronous paths, and must be either used or not used for
both paths.
The delay values are set up in the silicon once at configura-
tion time—they are non-modifiable in device operation.
12
PAD
Figure
Figure 6: Programmable Fixed Input Delay Elements
6, the signal is first
Initial Delay
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The primary use for the input delay element is to adjust the
input delay path to ensure that there is no hold time require-
ment when using the input flip-flop(s) with a global clock.
The default value is chosen automatically by the Xilinx soft-
ware tools as the value depends on device size and the spe-
cific device edge where the flip-flop resides. The value set
by the Xilinx ISE software and the resulting effects on input
timing are reported using the
If the design uses a DCM in the clock path, then the delay
element can be safely set to zero because the
Delay-Locked Loop (DLL)
ensures that there is still no input hold time requirement.
Both asynchronous and synchronous values can be modi-
fied, which is useful where extra delay is required on clock
or data inputs, for example, in interfaces to various types of
RAM.
Asynchronous input (I)
IBUF_DELAY_VALUE
Synchronous input (IQ1)
Synchronous input (IQ2)
IFD_DELAY_VALUE
D Q
D Q
DS312-2_18_102306
Timing Analyzer
compensation automatically
DS312-2 (v3.6) May 29, 2007
Product Specification
tool.
R