XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 149

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 106: Switching Characteristics for the DFS (Continued)
Notes:
1.
2.
3.
4.
5.
Phase Shifter (PS)
Table 107: Recommended Operating Conditions for the PS in Variable Phase Mode
Table 108: Switching Characteristics for the PS in Variable Phase Mode
Notes:
1.
2.
3.
DS312-3 (v3.6) May 29, 2007
Product Specification
Lock Time
LOCK_FX
Phase Shifting Range
MAX_STEPS
FINE_SHIFT_RANGE_MIN
FINE_SHIFT_RANGE_MAX
Operating Frequency Ranges
PSCLK_FREQ
(F
Input Pulse Requirements
PSCLK_PULSE
PSCLK
The numbers in this table are based on the operating conditions set forth in
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Use the Virtex-II Jitter Calculator at http://www.xilinx.com/applications/web_ds_v2/jitter_calc.htm.or the jitter calculator included in
Clock Wizard/DCM Wizard. Output jitter includes 150 ps of input clock jitter.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies
a maximum jitter of "±[1% of CLKFX period + 300]". Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 300 ps] = ±400 ps.
The numbers in this table are based on the operating conditions set forth in
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, i.e., the PHASE_SHIFT
attribute is set to 0.
The DCM_DELAY_STEP values are provided at the bottom of
Symbol
)
(2)
Symbol
Symbol
R
(2)
Frequency for the PSCLK input
PSCLK pulse width as a percentage of the PSCLK period
The time from deassertion at the
DCM’s Reset input to the rising
transition at its LOCKED output. The
DFS asserts LOCKED when the
CLKFX and CLKFX180 signals are
valid. If using both the DLL and the
DFS, use the longer locking time.
Maximum allowed number of DCM_DELAY_STEP
steps for a given CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double the clock
effective clock period.
Minimum guaranteed delay for variable phase shifting
Maximum guaranteed delay for variable phase shifting
Description
Description
Description
www.xilinx.com
Table
5 MHz < F
104.
< 15 MHz
F
15 MHz
CLKIN
Table 76
CLKIN
>
and
Table 76
Table
Device
All
107.
and
40%
Min
1
±[INTEGER(20 • (T
Table
DCM_DELAY_STEP_MAX]
DCM_DELAY_STEP_MIN]
DC and Switching Characteristics
-5
Min
-
-
±[MAX_STEPS •
±[MAX_STEPS •
60%
Max
105.
Speed Grade
167
-5
Speed Grade
Max
450
5
40%
Min
CLKIN
1
Min
-
-
-4
– 3 ns))]
-4
Max
60%
167
Max
450
5
Units
MHz
Units
steps
Units
ns
ns
ms
μs
-
149