XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 108

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Functional Description
Start-Up
At the end of configuration, the FPGA automatically pulses
the Global Set/Reset (GSR) signal, placing all flip-flops in a
known state. After configuration completes, the FPGA
switches over to the user application loaded into the FPGA.
The sequence and timing of how the FPGA switches over is
programmable as is the clock source controlling the
sequence.
The default start-up sequence appears in
the Global Three-State signal (GTS) is released one clock
cycle after DONE goes High. This sequence allows the
DONE signal to enable or disable any external logic used
108
Start-Up Clock
Start-Up Clock
Figure 69: Default Start-Up Sequence
Figure
DONE
DONE
Phase
Phase
GWE
GWE
GTS
GTS
69, where
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DONE High
0
0
1
1
Default Cycles
Sync-to-DONE
during configuration before the user application in the FPGA
starts driving output signals. One clock cycle later, the Glo-
bal Write Enable (GWE) signal is released. This allows sig-
nals to propagate within the FPGA before any clocked
storage elements such as flip-flops and block ROM are
enabled.
The function of the dual-purpose I/O pins
VS[2:0], HSWAP, and A[23:0]
DONE pin goes High. When DONE is High, these pins
become user I/Os. Like all user-I/O pins, GTS controls
when the dual-purpose pins can drive out.
2
2
3
3
4
4
5
5
DS312-2_60_022305
6 7
6 7
,
DS312-2 (v3.6) May 29, 2007
also changes when the
Product Specification
,
such as M[2:0],
R