XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 11

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XC3S100E

Manufacturer Part Number
XC3S100E
Description
Spartan-3e Fpga Family Complete Data Sheet
Manufacturer
Xilinx Corp.
Datasheet

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DS312-2 (v3.6) May 29, 2007
Product Specification
Notes:
1.
2.
IDDRIN1
IDDRIN2
OTCLK1
OTCLK2
ICLK1
ICLK2
All IOB control and output path signals have an inverting polarity option wihtin the IOB.
IDDRIN1/IDDRIN2 signals shown with dashed lines connect to the adjacent IOB in a differential pair only, not to the FPGA fabric.
TCE
OCE
REV
IQ1
ICE
IQ2
T1
T2
SR
O1
O2
T
I
R
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
D
CE
CK
SR
SR REV
SR
SR REV
SR
SR REV
REV
REV
REV
Q
Q
Q
Q
Q
Q
Figure 5: Simplified IOB Diagram
TFF1
TFF2
OFF1
OFF2
IFF1
IFF2
Programmable
Programmable
www.xilinx.com
DDR
MUX
MUX
DDR
Delay
Delay
Three-state Path
Input Path
Output Path
Program-
Output
mable
Driver
Single-ended Standards
LVCMOS, LVTTL, PCI
Differential Standards
using V REF
Functional Description
Pull-Up
Down
Pull-
Keeper
Latch
DS312-2_19_110606
V
Pin
I/O Pin
from
Adjacent
IOB
ESD
ESD
V
REF
CCO
I/O
Pin
11

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