XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 111

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 68: Spartan-3E FPGA Bitstream Generator (BitGen) Options (Continued)
DS312-2 (v3.6) May 29, 2007
Product Specification
LCK_cycle
DonePin
DriveDone
DonePipe
ProgPin
TckPin
TdiPin
TdoPin
TmsPin
UserID
Option Name
R
Pins/Function
JTAG TDO pin
JTAG TMS pin
JTAG TCK pin
JTAG User ID
Configuration
JTAG TDI pin
PROG_B pin
DONE pin
DONE pin
DONE pin
Affected
register
Startup
DCMs,
0, 1, 2, 3,
(default)
Pulldown
Pulldown
Pulldown
Pulldown
Pullnone
Pullnone
Pullnone
Pullnone
Pullnone
Pullnone
NoWait
Values
Pullup
Pullup
Pullup
Pullup
Pullup
Pullup
4, 5, 6
string
User
Yes
Yes
No
No
The FPGA does not wait for selected DCMs to lock before completing configuration.
If one or more DCMs in the design have the STARTUP_WAIT attribute set to TRUE,
the FPGA waits for such DCMs to acquire their respective input clock and assert their
LOCKED output. This setting selects the Configuration Startup phase where the FPGA
waits for the DCMs to lock.
Internally connects a pull-up resistor between DONE pin and V
330 Ω pull-up resistor to V
No internal pull-up resistor on DONE pin. An external 330 Ω pull-up resistor to V
is required.
When configuration completes, the DONE pin stops driving Low and relies on an
external 330 Ω pull-up resistor to V
When configuration completes, the DONE pin actively drives High. When using this
option, an external pull-up resistor is no longer required. Only one device in an FPGA
daisy-chain should use this setting.
The input path from DONE pin input back to the Startup sequencer is not pipelined.
This option adds a pipeline register stage between the DONE pin input and the Startup
sequencer. Used for high-speed daisy-chain configurations when DONE cannot rise in
a single CCLK cycle. Releases GWE and GTS signals on the first rising edge of
StartupClk after the DONE pin input goes High.
Internally connects a pull-up resistor or between PROG_B pin and V
external 4.7 kΩ pull-up resistor to V
No internal pull-up resistor on PROG_B pin. An external 4.7 kΩ pull-up resistor to
V
Internally connects a pull-up resistor between JTAG TCK pin and V
Internally connects a pull-down resistor between JTAG TCK pin and GND.
No internal pull-up resistor on JTAG TCK pin.
Internally connects a pull-up resistor between JTAG TDI pin and V
Internally connects a pull-down resistor between JTAG TDI pin and GND.
No internal pull-up resistor on JTAG TDI pin.
Internally connects a pull-up resistor between JTAG TDO pin and V
Internally connects a pull-down resistor between JTAG TDO pin and GND.
No internal pull-up resistor on JTAG TDO pin.
Internally connects a pull-up resistor between JTAG TMS pin and V
Internally connects a pull-down resistor between JTAG TMS pin and GND.
No internal pull-up resistor on JTAG TMS pin.
The 32-bit JTAG User ID register value is loaded during configuration. The default
value is all ones, 0xFFFF_FFFF hexadecimal. To specify another value, enter an
8-character hexadecimal value.
CCAUX
is required.
www.xilinx.com
CCAUX
is still recommended.
CCAUX
CCAUX
Description
for a valid logic High.
is still recommended.
Functional Description
CCAUX
CCAUX
CCAUX
CCAUX
CCAUX
CCAUX
. An external
.
.
.
.
. An
CCAUX
111