XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 159

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 119: Timing for Byte-wide Peripheral Interface (BPI) Configuration Mode (Continued)
Table 120: Configuration Timing Requirements for Attached Parallel NOR Flash
Table 121: MultiBoot Trigger (MBT) Timing
DS312-3 (v3.6) May 29, 2007
Product Specification
Notes:
1.
2.
3.
Notes:
1.
T
T
T
T
(t
T
(t
T
(t
T
(t
t
FHQV
Symbol
Symbol
Symbol
OE
ACC
CCO
DCC
CCD
CE
ELQV
GLQV
AVQV
BYTE
FLQV,
T
These requirements are for successful FPGA configuration in BPI mode, where the FPGA provides the CCLK frequency. The post
configuration timing can be different to support the specific needs of the application loaded into the FPGA and the resulting clock source.
Subtract additional printed circuit board routing delay as required by the application.
The initial BYTE# timing can be extended using an external, appropriately sized pull-down resistor on the FPGA’s LDC2 pin. The resistor
value also depends on whether the FPGA’s HSWAP pin is High or Low.
MultiBoot re-configuration starts on the rising edge after MBT is Low for at least the prescribed minimum period.
MBT
)
)
)
)
R
Address A[23:0] outputs valid after CCLK falling edge
Setup time on D[7:0] data inputs before CCLK falling edge
Hold time on D[7:0] data inputs after CCLK falling edge
Parallel NOR Flash PROM chip-select time
Parallel NOR Flash PROM output-enable time
Parallel NOR Flash PROM read access time
For x8/x16 PROMs only: BYTE# to output valid
time
MultiBoot Trigger (MBT) Low pulse width required to initiate
MultiBoot reconfiguration
(3)
Description
Description
Description
www.xilinx.com
T
ACC
≤
T
CCLKn min
T
T
T
BYTE
CE
OE
Requirement
(
≤
≤
Minimum
≤
)
T
DC and Switching Characteristics
T
–
300
T
INITADDR
INITADDR
Minimum
T
INITADDR
CCO
–
See
See
See
T
DCC
Maximum
Maximum
Table 115
Table 115
Table 115
–
∞
PCB
Units
Units
Units
ns
ns
ns
ns
ns
159