XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 39

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Block RAM Port Signal Definitions
DS312-2 (v3.6) May 29, 2007
Product Specification
Caution!
RAMB16_S[w
RAMB16_S[w] with their associated signals are shown in
Figure 32a
defined in
SSR) on the block RAM are active High. However, optional
Notes:
1.
2.
3.
4.
DIA[w
DIB[w
ADDRA[r
ADDRB[r
DIPB[p
DIPA[p
w
p
r
The control signals CLK, WE, EN, and SSR on both ports have the option of inverted polarity.
A
A
A
and r
A
B
and p
R
and w
–p
–p
Table
Representations of the dual-port primitive
and
SSRA
A
A
A
SSRB
B
B
B
CLKA
CLKB
B
WEA
WEB
–1:0]
–1:0]
–1:0]
–1:0]
–1:0]
–1:0]
A
ENA
ENB
B
B
are integers representing the address bus width at ports A and B, respectively.
]_S[w
are integers that indicate the number of data path lines serving as parity bits.
Figure
23. The control signals (WE, EN, CLK, and
are integers representing the total data path width (i.e., data bits plus parity bits) at Ports A and B, respectively.
B
] and the single-port primitive
32b, respectively. These signals are
RAMB16_S
(a) Dual-Port
W A
_S
W B
Figure 32: Block RAM Primitives
DOPA[p
DOA[w
DOPB[p
DOB[w
A
B
A
–p
B
–p
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–1:0]
–1:0]
A
B
–1:0]
–1:0]
inverters on the control signals change the polarity of the
active edge to active Low.
!
ADDR[r–1:0]
DI[w–p–1:0]
DIP[p–1:0]
Whenever a block RAM port is enabled (ENA or ENB
= High), all address transitions must meet the data
sheet setup and hold times with respect to the port
clock (CLKA or CLKB), as shown in
page
RAM read output is of no interest.
SSR
CLK
WE
144.This requirement must be met even if the
EN
(b) Single-Port
DESIGN NOTE:
RAMB16_Sw
Functional Description
DOP[p–1:0]
DO[w–p–1:0]
Table 102,
DS312-2_03_111105
39