XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 72

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Functional Description
Table 48: Pull-up or Pull-down Values for HSWAP, M[2:0], and VS[2:0]
The Configuration section provides detailed schematics for
each configuration mode. The schematics indicate the
required logic values for HSWAP, M[2:0], and VS[2:0] but
do not specify how the application provides the logic Low or
High value. The HSWAP, M[2:0], and VS[2:0] pins can be
either dedicated or reused by the FPGA application.
Dedicating the HSWAP, M[2:0], and VS[2:0] Pins
If the HSWAP, M[2:0], and VS[2:0] pins are not required by
the FPGA design after configuration, simply connect these
pins directly to the V
appropriate configuration schematic.
Reusing HSWAP, M[2:0], and VS[2:0] After Config-
uration
To reuse the HSWAP, M[2:0], and VS[2:0] pin after configu-
ration, use pull-up or pull-down resistors to define the logic
values shown in the appropriate configuration schematic.
The logic level on HSWAP dictates how to define the logic
levels on M[2:0] and VS[2:0], as shown in
application requires HSWAP to be High, the HSWAP pin is
pulled High using an external 3.3 to 4.7 kΩ resistor to
72
HSWAP Value
0
1
Enabled
Disabled
during Configuration
I/O Pull-up Resistors
CCO
or GND supply rail shown in the
Table
Pulled High via an internal pull-up
resistor to the associated V
supply. No external pull-up
resistor is necessary.
Pulled High using a 3.3 to 4.7 kΩ
resistor to the associated V
supply.
48. If the
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Required Resistor Value to Define Logic Level on
High
VCCO_0. If the application requires HSWAP to be Low dur-
ing configuration, then HSWAP is either connected to GND
or pulled Low using an appropriately sized external
pull-down resistor to GND. When HSWAP is Low, its pin has
an internal pull-up resistor to VCCO_0. The external
pull-down resistor must be strong enough to define a logic
Low on HSWAP for the I/O standard used during configura-
tion. For 2.5V or 3.3V I/O, the pull-down resistor is 560 Ω or
lower. For 1.8V I/O, the pull-down resistor is 1.1 kΩ or
lower.
Once HSWAP is defined, use
values for M[2:0] and VS[2:0].
Use the weakest external pull-up or pull-down resistor value
allowed by the application. The resistor must be strong
enough to define a logic Low or High during configuration.
However, when driving the HSWAP, M[2:0], or VS[2:0] pins
after configuration, the output driver must be strong enough
to overcome the pull-up or pull-down resistor value and
generate the appropriate logic levels. For example, to over-
come a 560 Ω pull-down resistor, a 3.3V FPGA I/O pin must
use a 6 mA or stronger driver.
HSWAP, M[2:0], or VS[2:0]
CCO
CCO
Pulled Low using an appropriately sized
pull-down resistor to GND.
For a 2.5V or 3.3V interface: R < 560 Ω .
For a 1.8V interface: R < 1.1 kΩ .
Pulled Low using a 3.3 to 4.7 kΩ resistor
to GND.
Table 48
DS312-2 (v3.6) May 29, 2007
Low
Product Specification
to define the logic
R