XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 200

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Pinout Descriptions
User I/Os by Bank
Table
available user-I/O pins are distributed between the four I/O
banks on the FT256 package.
Table 143: User I/Os Per Bank on XC3S250E in the FT256 Package
Table 144: User I/Os Per Bank on XC3S500E in the FT256 Package
.
Table 145: User I/Os Per Bank on XC3S1200E in the FT256 Package
200
Notes:
1.
2.
Notes:
1.
2.
Notes:
1.
2.
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Top
Right
Bottom
Left
TOTAL
Package
Package
Package
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Some VREF and CLK pins are on INPUT pins.
The eight global clock pins in this bank have optional functionality during configuration and are counted in the DUAL column.
Edge
Edge
Edge
143,
Table
144, and
I/O Bank
I/O Bank
I/O Bank
0
1
2
3
0
1
2
3
0
1
2
3
Table 145
Maximum
Maximum
Maximum
172
190
190
I/O
I/O
I/O
44
42
44
42
46
48
48
48
46
48
48
48
indicate how the
I/O
I/O
I/O
20
10
24
62
22
15
11
28
76
24
14
13
27
78
8
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The XC3S250E FPGA in the FT256 package has 18 uncon-
nected balls, labeled with an “N.C.” type. These pins are
also indicated with the black diamond ( ) symbol in
Figure
INPUT
INPUT
INPUT
10
33
10
33
31
7
9
7
7
9
7
8
8
7
8
All Possible I/O Pins by Type
All Possible I/O Pins by Type
All Possible I/O Pins by Type
86.
DUAL
DUAL
DUAL
21
24
46
21
24
46
21
24
46
1
0
1
0
1
0
VREF
VREF
VREF
DS312-4 (v3.6) May 29, 2007
15
19
19
5
4
3
3
5
5
4
5
5
5
4
5
(1)
Product Specification
(1)
(1)
CLK
CLK
CLK
0
0
0
0
0
0
16
16
16
8
8
(2)
(2)
8
8
8
8
(2)
(2)
(2)
(2)
(1)
(1)
(1)
R