XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 138

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

DC and Switching Characteristics
Simultaneously Switching Output Guidelines
This section provides guidelines for the recommended max-
imum allowable number of Simultaneous Switching Outputs
(SSOs). These guidelines describe the maximum number
of user I/O pins of a given output signal standard that should
simultaneously switch in the same direction, while maintain-
ing a safe level of switching noise. Meeting these guidelines
for the stated test conditions ensures that the FPGA oper-
ates free from the adverse effects of ground and power
bounce.
Ground or power bounce occurs when a large number of
outputs simultaneously switch in the same direction. The
output drive transistors all conduct current to a common
voltage rail. Low-to-High transitions conduct to the V
rail; High-to-Low transitions conduct to the GND rail. The
resulting cumulative current transient induces a voltage dif-
ference across the inductance that exists between the die
pad and the power supply or ground return. The inductance
is associated with bonding wires, the package lead frame,
and any other signal routing inside the package. Other vari-
ables contribute to SSO noise levels, including stray induc-
tance on the PCB as well as capacitive loading at receivers.
Any SSO-induced voltage consequently affects internal
switching noise margins and ultimately signal quality.
Table 95
lines. For each device/package combination,
Table 95: Equivalent V
138
XC3S100E
XC3S250E
XC3S500E
XC3S1200E
XC3S1600E
Device
and
Table 96
VQ100
2
2
-
-
-
provide the essential SSO guide-
CCO
/GND Pairs per Bank
CP132
2
2
2
-
-
Table 95
TQ144
2
2
-
-
-
Package Style (including Pb-free)
www.xilinx.com
CCO
pro-
PQ208
vides the number of equivalent V
output signal standard and drive strength,
mends the maximum number of SSOs, switching in the
same direction, allowed per V
bank. The guidelines in
age style. Multiply the appropriate numbers from
and
allowed within an I/O bank. Exceeding these SSO guide-
lines might result in increased power or ground bounce,
degraded signal integrity, or increased system jitter.
The recommended maximum SSO values assumes that the
FPGA is soldered on the printed circuit board and that the
board uses sound design practices. The SSO values do not
apply for FPGAs mounted in sockets, due to the lead induc-
tance introduced by the socket.
The number of SSOs allowed for quad-flat packages (VQ,
TQ, PQ) is lower than for ball grid array packages (FG) due
to the larger lead inductance of the quad-flat packages. The
results for chip-scale packaging (CP132) are better than
quad-flat packaging but not as high as for ball grid array
packaging. Ball grid array packages are recommended for
applications with a large number of simultaneously switch-
ing outputs.
3
3
-
-
-
SSO
Table 96
MAX
FT256
/IO Bank =
4
4
4
-
-
to calculate the maximum number of SSOs
FG320
Table 95
Table 96
5
5
5
-
-
CCO
DS312-3 (v3.6) May 29, 2007
x
CCO
are categorized by pack-
/GND pair within an I/O
Table 96
FG400
/GND pairs. For each
Product Specification
6
6
-
-
-
Table 96
FG484
Table 95
recom-
7
-
-
-
-
R