XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 116

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Functional Description
Revision History
The following table shows the revision history for this document.
116
03/01/05
03/21/05
11/23/05
03/22/06
04/10/06
05/19/06
05/30/06
10/02/06
Date
Version
3.2.1
1.0
1.1
2.0
3.0
3.1
3.2
3.3
Initial Xilinx release.
Updated
Updated values of
configuration bitstream sizes for XC3S250E through XC3S1600E in
and
Limitations when Reprogramming via JTAG if FPGA Set for BPI
0 limitations when
Interaction
(PS)
Added
M[2:0], and VS[2:0] Pins
vendors in
‘D’-series DataFlash. Updated the
Power-On Precautions if PROM Supply is Last in
BPI Mode Interaction with Right and Bottom Edge Global Clock Inputs
configuration mode topic. Updated and amplified
Production Stepping
Upgraded data sheet status to Preliminary. Updated
clarification that Input-only pins also have
about address setup and hold requirements to
differences between ISE 8.1i, Service Pack 3 and earlier software to
VARIABLE Phase Shift
Connections
behavior to
resistors unaffected by HSWAP in
XC3S1600E in
SPI PROMs can be used in Commercial temperature range applications in
Updated
MultiBoot Option
Daisy-Chaining
Pumps or Free-Running
Table
Updated
electrical connectivity and corrected left- and right-edge DCM coordinates. Updated
Table
Corrected the coordinate locations for the associated BUFGMUX primitives in
Updated
Made further clarifying changes to
to DCMs. Added Atmel AT45DBxxxD-series DataFlash serial PROMs to
intermediate FPGAs in a BPI-mode, multi-FPGA configuration daisy-chain must be from either the
Spartan-3E or the Virtex-5 FPGA families (see BPI Daisy-Chaining). Added
to Communicate to a Configured FPGA
Clarified which Spartan-3E FPGA product options support the Readback feature, shown in
Corrected various typos and incorrect links.
Clarified that the block RAM
Industrial temperature range.
Table
portion. Corrected and enhanced the clock infrastructure diagram in
70. Updated
31, and
CCLK Design Considerations
Figure
Figure
JTAG User ID
Table 41
59. Added
Table 52
Pin Behavior During
section. Updated
Table 32
and
Table
45. Modified title on
56. Updated
section. Updated JTAG revision codes in
to show that the I0-input is the preferred connection to a BUFGMUX.
Daisy-Chaining
Clock
On-Chip Differential Termination
section. Added design note about BPI daisy-chaining software support to BPI
Software Version
and
DLL Performance Differences Between
44,
section.
to show the specific clock line driven by the associated BUFGMUX primitive.
information. Clarified Note 1,
Table
Mode. Added message about using GCLK1 in
www.xilinx.com
Table
Inputs. Updated
section. Added Spansion, Winbond, and Macronix to list of SPI Flash
Oscillators. Updated information on production stepping differences in
Readback
Dynamically Loading Multiple Configuration Images Using
Digital Clock Managers (DCMs)
55. Clarified that SPI mode configuration supports Atmel ‘C’- and
50,
Configuration. Highlighted which pins have configuration pull-up
Table
Figure
Programming Support
Table
in SPI configuration mode. Added
Table 39
Requirements.
section. Added
feature is available either on the -5 speed grade or the
45. Updated bitstream image sizes for the XC3S1200E and
56, and
46, showing both direct inputs to BUFGMUX primitives and
Pull-Up and Pull-Down
Design. Minor updates to
Figure
Revision
and
Block
Powering Spartan-3E FPGAs
Table
45. Added additional information on HSWAP
Table
Input Delay Functions
Sequence,
RAM. Added warning message about software
Figure
resistors. Updated
Design Considerations for the HSWAP,
59. Clarified that ‘B’-series Atmel DataFlash
44.
Table
section for SPI Flash PROMs. Added
5. Clarified that
Steppings. Added
section, especially
66. Added
Compatible Flash
Resistors. Added design note
Configuration. Added Stepping
Table
FIXED Phase Shift Mode
Figure 67
Multiplier/Block RAM
DS312-2 (v3.6) May 29, 2007
DLL Clock Input
Table
Table
Figure 45
44,
Table 52
No Internal Charge
sections to BPI
Figure 45
and
Using JTAG Interface
Table 31
Table
52. Added details that
Product Specification
and
7. Updated
section. Added
Figure
Phase Shifter
Stepping 0
Figure
and
50,
Table
and
Families, and
and
shows
Table
Table
6. Added
Figure
30,
Table
68.
Table
56,
41.
and
54.
32.
67.
R