XC3S100E Xilinx Corp., XC3S100E Datasheet - Page 81

• Manufacturer Part Number: XC3S100E
• Description: Spartan-3e Fpga Family Complete Data Sheet
• Manufacturer: Xilinx Corp.

Table 54: Serial Peripheral Interface (SPI) Connections
DS312-2 (v3.6) May 29, 2007
Product Specification
HSWAP
M[2:0]
VS[2:0]
MOSI
DIN
CSO_B
CCLK
DOUT
Pin Name
P
S
R
Direction
Output
Output
Output
Output
FPGA
Input
Input
Input
Input
User I/O Pull-Up Control. When Low
during configuration, enables pull-up
resistors in all I/O pins to respective I/O
bank V
0: Pull-ups during configuration
1: No pull-ups
Mode Select. Selects the FPGA
configuration mode. See
Considerations for the HSWAP,
M[2:0], and VS[2:0]
Variant Select. Instructs the FPGA how
to communicate with the attached SPI
Flash PROM. See
Considerations for the HSWAP,
M[2:0], and VS[2:0]
Serial Data Output.
Serial Data Input.
Chip Select Output. Active Low.
Configuration Clock. Generated by
FPGA internal oscillator. Frequency
controlled by ConfigRate bitstream
generator option. If CCLK PCB trace is
long or has multiple connections,
terminate this output to maintain signal
integrity. See
Considerations.
Serial Data Output.
CCO
input.
CCLK Design
Description
Design
Pins.
Pins.
Design
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Drive at valid logic level
throughout configuration.
M2 = 0, M1 = 0, M0 = 1.
Sampled when INIT_B goes
High.
Must be at the logic levels
shown in
when INIT_B goes High.
FPGA sends SPI Flash memory
read commands and starting
address to the PROM’s serial
data input.
FPGA receives serial data from
PROM’s serial data output.
Connects to the SPI Flash
PROM’s chip-select input. If
HSWAP = 1, connect this signal
to a 4.7 kΩ pull-up resistor to
3.3V.
Drives PROM’s clock input.
Actively drives. Not used in
single-FPGA designs. In a
daisy-chain configuration, this
pin connects to DIN input of the
next FPGA in the chain.
During Configuration
Table
52. Sampled
User I/O
User I/O
User I/O
User I/O
User I/O
Drive CSO_B High after
configuration to disable the
SPI Flash and reclaim the
MOSI, DIN, and CCLK pins.
Optionally, re-use this pin
and MOSI, DIN, and CCLK
to continue communicating
with SPI Flash.
User I/O
User I/O
Functional Description
After Configuration
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